| /dalvik/vm/mterp/armv5te/ |
| OP_INT_TO_CHAR.S | 2 %include "armv5te/unop.S" {"preinstr":"mov r0, r0, asl #16", "instr":"mov r0, r0, lsr #16"}
|
| OP_USHR_INT.S | 2 %include "armv5te/binop.S" {"preinstr":"and r1, r1, #31", "instr":"mov r0, r0, lsr r1"}
|
| OP_USHR_INT_2ADDR.S | 2 %include "armv5te/binop2addr.S" {"preinstr":"and r1, r1, #31", "instr":"mov r0, r0, lsr r1"}
|
| OP_USHR_INT_LIT8.S | 2 %include "armv5te/binopLit8.S" {"preinstr":"and r1, r1, #31", "instr":"mov r0, r0, lsr r1"}
|
| OP_MOVE.S | 4 mov r1, rINST, lsr #12 @ r1<- B from 15:12
5 mov r0, rINST, lsr #8 @ r0<- A from 11:8
|
| OP_USHR_LONG_2ADDR.S | 7 mov r9, rINST, lsr #8 @ r9<- A+
8 mov r3, rINST, lsr #12 @ r3<- B
15 mov r0, r0, lsr r2 @ r0<- r2 >> r2
20 movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32)
21 mov r1, r1, lsr r2 @ r1<- r1 >>> r2
|
| OP_IPUT_OBJECT_QUICK.S | 5 mov r2, rINST, lsr #12 @ r2<- B
9 mov r2, rINST, lsr #8 @ r2<- A(+)
17 strneb r2, [r2, r3, lsr #GC_CARD_SHIFT] @ mark card based on obj head
|
| OP_ARRAY_LENGTH.S | 5 mov r1, rINST, lsr #12 @ r1<- B
6 mov r2, rINST, lsr #8 @ r2<- A+
|
| OP_CONST_16.S | 4 mov r3, rINST, lsr #8 @ r3<- AA
|
| OP_RETURN.S | 9 mov r2, rINST, lsr #8 @ r2<- AA
|
| /dalvik/vm/mterp/armv6t2/ |
| OP_USHR_INT_2ADDR.S | 2 %include "armv6t2/binop2addr.S" {"preinstr":"and r1, r1, #31", "instr":"mov r0, r0, lsr r1"}
|
| /external/skia/src/core/asm/ |
| s32a_d565_opaque.S | 36 mov lr, r1, lsr #24
42 moveq r2, r1, lsr #5
46 orreq r3, r3, r6, lsr #27
52 mov r5, r3, lsr #24
54 mov lr, r6, lsr #24
57 mov r1, r3, lsr #5
61 mov r1, r3, lsr #11
62 add r2, r2, r2, lsr #6
65 add r2, r5, r2, lsr #6
68 add r1, r1, r1, lsr #
[all...] |
| /external/llvm/test/CodeGen/Hexagon/ |
| remove_lsr.ll | 4 ; CHECK-NOT: lsr(r{{[0-9]+}}:{{[0-9]+}}, #32)
5 ; CHECK-NOT: lsr(r{{[0-9]+}}:{{[0-9]+}}, #32)
8 ; r17:16 = lsr(r11:10, #32)
11 ; r17:16 = lsr(r11:10, #32)
13 ; This makes the lsr instruction dead and it gets removed subsequently
32 %lsr.iv42 = phi i32 [ %lsr.iv.next, %for.body ], [ 2, %entry ]
33 %lsr.iv40 = phi i8* [ %scevgep41, %for.body ], [ %scevgep39, %entry ]
34 %lsr.iv37 = phi i8* [ %scevgep38, %for.body ], [ %scevgep36, %entry ]
35 %lsr.iv33 = phi %union.vect32* [ %scevgep34, %for.body ], [ %scevgep32, %entry
[all...] |
| /external/llvm/test/MC/ARM/ |
| arm_addrmode2.s | 5 @ CHECK: ldrt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xb0,0xe6]
8 @ CHECK: ldrbt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xf0,0xe6]
11 @ CHECK: strt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xa0,0xe6]
14 @ CHECK: strbt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xe0,0xe6]
17 ldrt r1, [r0], r2, lsr #3
20 ldrbt r1, [r0], r2, lsr #3
23 strt r1, [r0], r2, lsr #3
26 strbt r1, [r0], r2, lsr #3
30 @ CHECK: ldr r1, [r0, r2, lsr #3]! @ encoding: [0xa2,0x11,0xb0,0xe7]
31 @ CHECK: ldrb r1, [r0, r2, lsr #3]! @ encoding: [0xa2,0x11,0xf0,0xe7
[all...] |
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p10/src_gcc/ |
| armVCM4P10_InterpolateLuma_Align_unsafe_s.S | 36 LSR r7,r7,#8
38 LSR r10,r10,#8
40 LSR r11,r11,#8
48 LSR r7,r7,#16
50 LSR r10,r10,#16
52 LSR r11,r11,#16
60 LSR r7,r7,#24
62 LSR r10,r10,#24
64 LSR r11,r11,#24
95 ORR r7,r10,r7,LSR #
[all...] |
| armVCM4P10_InterpolateLuma_Copy_unsafe_s.S | 40 LSR r4,r4,#8
43 LSR r8,r8,#8
50 LSR r4,r4,#8
53 LSR r8,r8,#8
62 LSR r4,r4,#16
65 LSR r8,r8,#16
72 LSR r4,r4,#16
75 LSR r8,r8,#16
84 LSR r4,r4,#24
87 LSR r8,r8,#2
[all...] |
| armVCM4P10_InterpolateLuma_DiagCopy_unsafe_s.S | 33 AND r11,r12,r11,LSR #5
34 AND r10,r12,r10,LSR #5
35 AND r5,r12,r5,LSR #5
36 AND r4,r12,r4,LSR #5
67 AND r11,r12,r11,LSR #5
68 AND r10,r12,r10,LSR #5
69 AND r5,r12,r5,LSR #5
70 AND r4,r12,r4,LSR #5
89 AND r11,r12,r11,LSR #5
90 AND r10,r12,r10,LSR #
[all...] |
| /system/core/libpixelflinger/ |
| col32cb16blend.S | 42 mov r5, r1, lsr #24 // shift down alpha
44 add r5, r5, r5, lsr #7 // add in top bit
47 and r12, r9, r1, lsr #8 // extract green
48 and r4, r9, r1, lsr #16 // extract blue
52 mov r9, r9, lsr #2 // create dest green mask
57 mov r6, r8, lsr #11 // extract dest red
58 and r7, r9, r8, lsr #5 // extract dest green
65 mov r6, r6, lsr #8 // shift down red
66 mov r7, r7, lsr #8 // shift down green
69 orr r6, r8, lsr #8 // shift blue into 56
[all...] |
| /dalvik/vm/compiler/template/armv5te/ |
| TEMPLATE_USHR_LONG.S | 9 mov r0, r0, lsr r2 @ r0<- r2 >> r2
13 movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32)
14 mov r1, r1, lsr r2 @ r1<- r1 >>> r2
|
| /external/openssl/crypto/modes/asm/ |
| ghash-armv4.s | 50 eor r4,r8,r4,lsr#4
54 eor r5,r9,r5,lsr#4
56 eor r6,r10,r6,lsr#4
58 eor r7,r11,r7,lsr#4
70 eor r4,r8,r4,lsr#4
72 eor r5,r9,r5,lsr#4
75 eor r6,r10,r6,lsr#4
78 eor r7,r11,r7,lsr#4
85 eor r4,r8,r4,lsr#4
88 eor r5,r9,r5,lsr#
[all...] |
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm11/vc/m4p10/src/ |
| armVCM4P10_InterpolateLuma_Copy_unsafe_s.s | 77 MOV x0, x0, LSR #8
80 MOV x2, x2, LSR #8
87 MOV x0, x0, LSR #8
90 MOV x2, x2, LSR #8
100 MOV x0, x0, LSR #16
103 MOV x2, x2, LSR #16
111 MOV x0, x0, LSR #16
114 MOV x2, x2, LSR #16
124 MOV x0, x0, LSR #24
127 MOV x2, x2, LSR #2
[all...] |
| armVCM4P10_InterpolateLuma_DiagCopy_unsafe_s.s | 87 AND Temp4, r0x00ff00ff, Temp4, LSR #5
88 AND Temp3, r0x00ff00ff, Temp3, LSR #5
89 AND Temp2, r0x00ff00ff, Temp2, LSR #5
90 AND Temp1, r0x00ff00ff, Temp1, LSR #5
127 AND Temp4, r0x00ff00ff, Temp4, LSR #5
128 AND Temp3, r0x00ff00ff, Temp3, LSR #5
129 AND Temp2, r0x00ff00ff, Temp2, LSR #5
130 AND Temp1, r0x00ff00ff, Temp1, LSR #5
155 AND Temp4, r0x00ff00ff, Temp4, LSR #5
156 AND Temp3, r0x00ff00ff, Temp3, LSR #5
[all...] |
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p10/src/ |
| armVCM4P10_InterpolateLuma_Copy_unsafe_s.s | 77 MOV x0, x0, LSR #8
80 MOV x2, x2, LSR #8
87 MOV x0, x0, LSR #8
90 MOV x2, x2, LSR #8
100 MOV x0, x0, LSR #16
103 MOV x2, x2, LSR #16
111 MOV x0, x0, LSR #16
114 MOV x2, x2, LSR #16
124 MOV x0, x0, LSR #24
127 MOV x2, x2, LSR #2
[all...] |
| armVCM4P10_InterpolateLuma_DiagCopy_unsafe_s.s | 87 AND Temp4, r0x00ff00ff, Temp4, LSR #5
88 AND Temp3, r0x00ff00ff, Temp3, LSR #5
89 AND Temp2, r0x00ff00ff, Temp2, LSR #5
90 AND Temp1, r0x00ff00ff, Temp1, LSR #5
127 AND Temp4, r0x00ff00ff, Temp4, LSR #5
128 AND Temp3, r0x00ff00ff, Temp3, LSR #5
129 AND Temp2, r0x00ff00ff, Temp2, LSR #5
130 AND Temp1, r0x00ff00ff, Temp1, LSR #5
155 AND Temp4, r0x00ff00ff, Temp4, LSR #5
156 AND Temp3, r0x00ff00ff, Temp3, LSR #5
[all...] |
| /external/openssl/crypto/bn/asm/ |
| armv4-gf2m.s | 55 and r9,r12,r0,lsr#1
57 and r8,r12,r0,lsr#4
59 and r9,r12,r0,lsr#7
62 mov r4,r7,lsr#29
65 and r8,r12,r0,lsr#10
67 eor r4,r4,r6,lsr#26
70 and r9,r12,r0,lsr#13
72 eor r4,r4,r7,lsr#23
75 and r8,r12,r0,lsr#16
77 eor r4,r4,r6,lsr#2
[all...] |
