| /external/llvm/lib/Target/X86/ |
| X86InstrSystem.td | 64 def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iret{w}", [], IIC_IRET>, OpSize;
78 "in{w}\t{%dx, %ax|AX, DX}", [], IIC_IN_RR>, OpSize;
88 "in{w}\t{$port, %ax|AX, $port}", [], IIC_IN_RI>, OpSize;
98 "out{w}\t{%ax, %dx|DX, AX}", [], IIC_OUT_RR>, OpSize;
108 "out{w}\t{%ax, $port|$port, AX}", [], IIC_OUT_IR>, OpSize;
114 def IN16 : I<0x6D, RawFrm, (outs), (ins), "ins{w}", [], IIC_INS>, OpSize;
159 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>, OpSize;
166 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSize;
173 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize;
180 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>, OpSize;
[all...] |
| X86InstrFormats.td | 97 class OpSize { bit hasOpSizePrefix = 1; }
319 !if(hasOpSizePrefix /* OpSize */, [UseSSE2], [UseSSE1]));
329 let Predicates = !if(hasOpSizePrefix /* OpSize */, [HasSSE2], [HasSSE1]);
337 !if(hasOpSizePrefix /* OpSize */, [UseSSE2], [UseSSE1]));
380 // PDI - SSE2 instructions with TB and OpSize prefixes.
381 // PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
383 // VPDI - SSE2 instructions with TB and OpSize prefixes in AVX form.
403 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, TB, OpSize,
407 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, TB, OpSize,
420 OpSize, Requires<[HasAVX]>
[all...] |
| X86InstrShiftRotate.td | 25 [(set GR16:$dst, (shl GR16:$src1, CL))], IIC_SR>, OpSize;
42 OpSize;
57 "shl{w}\t$dst", [], IIC_SR>, OpSize;
75 OpSize;
91 OpSize;
110 OpSize;
127 [(set GR16:$dst, (srl GR16:$src1, CL))], IIC_SR>, OpSize;
142 IIC_SR>, OpSize;
157 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))], IIC_SR>, OpSize;
174 OpSize;
[all...] |
| X86InstrVMX.td | 20 "invept\t{$src2, $src1|$src1, $src2}", []>, OpSize, T8,
23 "invept\t{$src2, $src1|$src1, $src2}", []>, OpSize, T8,
27 "invvpid\t{$src2, $src1|$src1, $src2}", []>, OpSize, T8,
30 "invvpid\t{$src2, $src1|$src1, $src2}", []>, OpSize, T8,
35 "vmclear\t$vmcs", []>, OpSize, TB;
|
| X86InstrControl.td | 29 [], IIC_RET>, OpSize;
35 [], IIC_RET_IMM>, OpSize;
39 "{l}ret{w|f}", [], IIC_RET>, OpSize;
45 "{l}ret{w|f}\t$amt", [], IIC_RET>, OpSize;
124 "ljmp{w}\t{$seg, $off|$off, $seg}", [], IIC_JMP_FAR_PTR>, OpSize;
132 "ljmp{w}\t{*}$dst", [], IIC_JMP_FAR_MEM>, OpSize;
166 IIC_CALL_FAR_PTR>, OpSize;
173 "lcall{w}\t{*}$dst", [], IIC_CALL_FAR_MEM>, OpSize;
181 "callw\t$dst", []>, OpSize;
|
| X86InstrExtension.td | 17 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
24 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
45 TB, OpSize;
49 TB, OpSize;
68 TB, OpSize;
72 TB, OpSize;
|
| X86InstrInfo.td | 741 "nop{w}\t$zero", [], IIC_NOP>, TB, OpSize;
[all...] |
| X86InstrArithmetic.td | 21 "lea{w}\t{$src|$dst}, {$dst|$src}", [], IIC_LEA_16>, OpSize;
61 [], IIC_MUL16_REG>, OpSize; // AX,DX = AX*GR16
87 [], IIC_MUL16_MEM>, OpSize; // AX,DX = AX*[mem16]
104 IIC_IMUL16_RR>, OpSize; // AX,DX = AX*GR16
118 "imul{w}\t$src", [], IIC_IMUL16_MEM>, OpSize;
139 TB, OpSize;
160 TB, OpSize;
187 IIC_IMUL16_RRI>, OpSize;
194 OpSize;
228 OpSize;
[all...] |
| X86InstrSSE.td | [all...] |
| X86InstrCMovSetCC.td | 25 IIC_CMOV16_RR>,TB,OpSize;
46 TB, OpSize;
|
| X86InstrMMX.td | 506 MMX_CVT_PD_ITINS, SSEPackedDouble>, TB, OpSize;
512 MMX_CVT_PD_ITINS, SSEPackedDouble>, TB, OpSize;
515 MMX_CVT_PD_ITINS, SSEPackedDouble>, TB, OpSize;
|
| X86InstrCompiler.td | 205 [(set GR16:$dst, 0)], IIC_ALU_NONMEM>, OpSize;
245 OpSize;
308 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize,
320 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize,
338 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize,
353 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize,
648 [], IIC_ALU_NONMEM>, OpSize, LOCK;
[all...] |
| /external/llvm/lib/Target/X86/Disassembler/ |
| X86DisassemblerDecoderCommon.h | 79 ENUM_ENTRY(IC_OPSIZE, 3, "requires an OPSIZE prefix, so " \
87 ENUM_ENTRY(IC_XD_OPSIZE, 3, "requires an OPSIZE prefix, so " \
89 ENUM_ENTRY(IC_XS_OPSIZE, 3, "requires an OPSIZE prefix, so " \
100 ENUM_ENTRY(IC_64BIT_REXW_XS, 6, "OPSIZE could mean a different " \
110 ENUM_ENTRY(IC_VEX_OPSIZE, 2, "requires VEX and the OpSize prefix") \
114 ENUM_ENTRY(IC_VEX_W_OPSIZE, 4, "requires VEX, W, and OpSize") \
118 ENUM_ENTRY(IC_VEX_L_OPSIZE, 4, "requires VEX, L, and OpSize") \
119 ENUM_ENTRY(IC_VEX_L_W_OPSIZE, 5, "requires VEX, L, W and OpSize")
|
| X86DisassemblerDecoder.c | 797 * We only need to do this if the instruction doesn't specify OpSize since
830 * allow OpSize anywhere (i.e., 16-bit operations) and that need it in a
832 * conservative, but in the specific case where OpSize is present but not
846 * ModRM required with OpSize but not present; give up and return version
847 * without OpSize set
[all...] |
| /dalvik/vm/compiler/codegen/mips/ |
| Codegen.h | 81 int displacement, int rSrc, OpSize size);
|
| Ralloc.h | 36 static inline RegisterClass dvmCompilerRegClassBySize(OpSize size)
|
| /dalvik/vm/compiler/codegen/ |
| Ralloc.h | 32 static inline RegisterClass dvmCompilerRegClassBySize(OpSize size)
222 int displacement, int rSrc, OpSize size);
|
| /external/llvm/utils/TableGen/ |
| DisassemblerEmitter.cpp | 38 /// instruction with an OPSIZE prefix and an XS prefix decodes the same way in
39 /// all cases as a 64-bit instruction with only OPSIZE set. (The XS prefix
|
| X86RecognizableInstr.h | 142 /// mandatory OpSize prefix.
146 /// @param hasOpSizePrefix Indicates whether the instruction has an OpSize
160 /// @param hasOpSizePrefix - Indicates whether the instruction has an OpSize
|
| X86RecognizableInstr.cpp | [all...] |
| /external/openssl/crypto/perlasm/ |
| x86gas.pl | 16 sub opsize() subroutine
42 if ($dst =~ m/^%/o) { $suffix=&opsize($dst); }
43 elsif ($src =~ m/^%/o) { $suffix=&opsize($src); }
|
| /frameworks/base/tools/obbtool/ |
| Main.cpp | 252 if (strncmp(op, name, opsize)) { \
260 const int opsize = strlen(op); local
|
| /dalvik/vm/compiler/codegen/arm/Thumb/ |
| Factory.cpp | 470 int rIndex, int rDest, int scale, OpSize size)
513 int rIndex, int rSrc, int scale, OpSize size)
577 OpSize size, int sReg)
698 int displacement, int rDest, OpSize size,
715 OpSize size)
808 int displacement, int rSrc, OpSize size)
|
| /dalvik/vm/compiler/codegen/mips/Mips32/ |
| Factory.cpp | 422 int rIndex, int rDest, int scale, OpSize size)
484 int rIndex, int rSrc, int scale, OpSize size)
594 OpSize size, int sReg)
703 int displacement, int rDest, OpSize size,
720 OpSize size)
812 int displacement, int rSrc, OpSize size)
|
| /dalvik/vm/compiler/codegen/arm/Thumb2/ |
| Factory.cpp | 714 int rIndex, int rDest, int scale, OpSize size)
778 int rIndex, int rSrc, int scale, OpSize size)
844 OpSize size, int sReg)
960 int displacement, int rDest, OpSize size,
978 OpSize size)
[all...] |
