Lines Matching refs:x8
49 #define TIMPANI_MREF_MREF_100UA_CUR_CONN_M 0x8
155 #define TIMPANI_TXADC3_EN_TXADC3_COMP_EN_M 0x8
199 #define TIMPANI_TXADC4_EN_TXADC4_COMP_EN_M 0x8
259 #define TIMPANI_TXFE1_TXFE1_IN_MIC2_CONN_M 0x8
302 #define TIMPANI_TXFE2_TXFE2_IN_MIC2_CONN_M 0x8
349 #define TIMPANI_TXFE12_ATEST_TXFE2_OUT_SHORT_TO_VICM_EN_M 0x8
424 #define TIMPANI_TXADC1_EN_TXADC1_COMP_EN_M 0x8
467 #define TIMPANI_TXADC2_EN_TXADC2_COMP_EN_M 0x8
620 #define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_STATE_RESET_M 0x8
716 #define TIMPANI_TXFE3_ATEST_TXFE4_OUT_SHORT_TO_VICM_EN_M 0x8
745 #define TIMPANI_TXFE_DIFF_SE_TXADC1_IN_MODE_M 0x8
792 #define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_25_2NS 0x8
911 #define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_EN_SOURCE_M 0x8
1200 #define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_2_5UA 0x8
1222 #define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_2_5UA 0x8
1301 #define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_VCM_BUFFER_EN_M 0x8
1347 #define TIMPANI_PA_LINE_AUXO_EN_LINE_VCM_BUFFER_EN_M 0x8
1394 #define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_REF_EN_M 0x8
1431 #define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_10_5 0x8
1497 #define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_10_5 0x8
1564 #define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_10_5 0x8
1635 #define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_10_5 0x8
1706 #define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_6_0DB 0x8
1729 #define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_6_0DB 0x8
1764 #define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_GAIN_M 0x8
1810 #define TIMPANI_PA_LINE_ST_CONN_LINE_R_IDAC_R_CONN_M 0x8
1854 #define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_INV_CONN_M 0x8
1897 #define TIMPANI_PA_HPH_ST_CONN_HPH_R_IDAC_R_CONN_M 0x8
1944 #define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_INV_CONN_M 0x8
2001 #define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_CIRCUIT_EN_M 0x8
2151 #define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CLK_SEL_LEFT_M 0x8
2190 #define TIMPANI_PA_CLASSD_L_SW_CTL_RESERVED_M 0x8
2241 #define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_8 0x8
2270 #define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_2303 0x8
2292 #define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_2303 0x8
2327 #define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CLK_SEL_RIGHT_M 0x8
2366 #define TIMPANI_PA_CLASSD_R_SW_CTL_RESERVED_M 0x8
2417 #define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_8 0x8
2446 #define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_2303 0x8
2469 #define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_2303 0x8
2494 #define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_50PER 0x8
2497 #define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_DET_EN_M 0x8
2605 #define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_GAIN_M 0x8
2719 #define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_SC_DET_M 0x8
2747 #define TIMPANI_PA_HPH_SC_STATUS_HPH_R_SC_DET_M 0x8
2894 #define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_L_CONN_M 0x8
2966 #define TIMPANI_ATEST_IDAC_ATEST2_LR_CONN_M 0x8
3010 #define TIMPANI_ATEST_PA1_ATEST_EARPA_IBTEST_VSS2P2_CONN_M 0x8
3047 #define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_NO_CONNECT_2 0x8
3070 #define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_NO_CONNECT_2 0x8
3107 #define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NREFIN_STG1OP_CONN_M 0x8
3141 #define TIMPANI_CDC_RESET_CTL_RX2_SOFT_RESET_M 0x8
3222 #define TIMPANI_CDC_CH_CTL_TX1_EN_R_M 0x8
3301 #define TIMPANI_CDC_GCTL1_RX1_PGA_UPDATE_R_M 0x8
3336 #define TIMPANI_CDC_ST_CTL_TX1_R_SIDETONE_UPDATE_M 0x8
3370 #define TIMPANI_CDC_BYPASS_CTL1_DITHER_BP_M 0x8
3400 #define TIMPANI_CDC_TESTMODE1_RX1_TEST_EN_L_M 0x8
3699 #define TIMPANI_CDC_ADC_CLK_EN_A_TX2_R_EN_M 0x8
3715 #define TIMPANI_CDC_ST_MIXING_TX2_R_M 0x8
3885 #define TIMPANI_CDC_GCTL2_RX2_PGA_UPDATE_R_M 0x8
3906 #define TIMPANI_CDC_BYPASS_CTL2_TX1_HPF_BP_R_M 0x8
3927 #define TIMPANI_CDC_BYPASS_CTL3_TX2_HPF_BP_R_M 0x8
3944 #define TIMPANI_CDC_BYPASS_CTL4_DITHER_BP_M 0x8
4000 #define TIMPANI_CDC_TESTMODE2_RX2_TEST_EN_L_M 0x8
4021 #define TIMPANI_CDC_PDM_OE_PDM_15_12_OE_M 0x8
4085 #define TIMPANI_CDC_ANC1_CTL1_ANC1_LR_EN_M 0x8
4259 #define TIMPANI_CDC_ANC2_CTL1_ANC2_LR_EN_M 0x8
4487 #define TIMPANI_CDC_COMP_CTL1_LO_R_EN_M 0x8
4581 #define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_LO_R_M 0x8
