Lines Matching refs:PhysicalReg_ESP
1059 load_effective_addr(-8, PhysicalReg_ESP, true, PhysicalReg_ESP, true);
1060 move_reg_to_mem(OpndSize_32, C_SCRATCH_2, isScratchPhysical, 4, PhysicalReg_ESP, true);
1061 move_reg_to_mem(OpndSize_32, exceptionPtrReg, true, 0, PhysicalReg_ESP, true);
1063 load_effective_addr(8, PhysicalReg_ESP, true, PhysicalReg_ESP, true);
1078 load_effective_addr(-8, PhysicalReg_ESP, true, PhysicalReg_ESP, true);
1079 move_reg_to_mem(OpndSize_32, immReg, true, 4, PhysicalReg_ESP, true);
1080 move_reg_to_mem(OpndSize_32, exceptionPtrReg, true, 0, PhysicalReg_ESP, true);
1082 load_effective_addr(8, PhysicalReg_ESP, true, PhysicalReg_ESP, true);
1145 load_effective_addr(-16, PhysicalReg_ESP, true, PhysicalReg_ESP, true);
1146 move_imm_to_mem(OpndSize_32, tSize, 8, PhysicalReg_ESP, true);
1147 move_imm_to_mem(OpndSize_32, firstKey, 4, PhysicalReg_ESP, true);
1151 move_imm_to_mem(OpndSize_32, (int)entries, 0, PhysicalReg_ESP, true);
1152 move_reg_to_mem(OpndSize_32, 1, false, 12, PhysicalReg_ESP, true);
1158 load_effective_addr(16, PhysicalReg_ESP, true, PhysicalReg_ESP, true);
1171 move_imm_to_mem(OpndSize_32, kSwitchOverflow, 0, PhysicalReg_ESP, true);
1210 load_effective_addr(-12, PhysicalReg_ESP, true, PhysicalReg_ESP, true);
1211 move_imm_to_mem(OpndSize_32, tSize, 4, PhysicalReg_ESP, true);
1215 move_imm_to_mem(OpndSize_32, (int)keys, 0, PhysicalReg_ESP, true);
1216 move_reg_to_mem(OpndSize_32, 1, false, 8, PhysicalReg_ESP, true);
1222 load_effective_addr(12, PhysicalReg_ESP, true, PhysicalReg_ESP, true);
1235 move_imm_to_mem(OpndSize_32, kSwitchOverflow, 0, PhysicalReg_ESP, true);
1439 load_effective_addr(4, PhysicalReg_ESP, true, PhysicalReg_ESP, true);
1461 load_effective_addr(4, PhysicalReg_ESP, true, PhysicalReg_ESP, true);
1505 load_effective_addr(-4, PhysicalReg_ESP, true, PhysicalReg_ESP, true);
1506 move_reg_to_mem(OpndSize_32, P_GPR_1, true, 0, PhysicalReg_ESP, true);
1508 load_effective_addr(4, PhysicalReg_ESP, true, PhysicalReg_ESP, true);
1534 move_mem_to_reg(OpndSize_32, offsetof(Thread, interpSave.bailPtr), PhysicalReg_EAX, true, PhysicalReg_ESP, true);
1535 move_reg_to_reg(OpndSize_32, PhysicalReg_ESP, true, PhysicalReg_EBP, true);
1541 move_reg_to_reg(OpndSize_32, PhysicalReg_EBP, true, PhysicalReg_ESP, true);
1542 move_mem_to_reg(OpndSize_32, 0, PhysicalReg_ESP, true, PhysicalReg_EBP, true);
1543 load_effective_addr(4, PhysicalReg_ESP, true, PhysicalReg_ESP, true);
1570 move_mem_to_reg(OpndSize_32, offsetof(Thread, interpSave.bailPtr), PhysicalReg_EAX, true, PhysicalReg_ESP, true);
1571 move_reg_to_reg(OpndSize_32, PhysicalReg_ESP, true, PhysicalReg_EBP, true);
1577 move_reg_to_reg(OpndSize_32, PhysicalReg_EBP, true, PhysicalReg_ESP, true);
1578 move_mem_to_reg(OpndSize_32, 0, PhysicalReg_ESP, true, PhysicalReg_EBP, true);
1579 load_effective_addr(4, PhysicalReg_ESP, true, PhysicalReg_ESP, true);
