Lines Matching refs:phy
83 * PHY definitions
259 /* Generic MII/PHY Registers */
294 /* ThunderLAN Specific MII/PHY Registers */
315 /* National Sem. & Level1 PHY id's */
591 ThunderLAN Driver PHY Layer Routines
605 * This function prints the registers a PHY (aka tranceiver).
612 u16 i, data0, data1, data2, data3, phy;
614 phy = priv->phy[priv->phyNum];
617 printk( "TLAN: Device %s, Unmanaged PHY.\n", dev->name );
618 } else if ( phy <= TLAN_PHY_MAX_ADDR ) {
619 printk( "TLAN: Device %s, PHY 0x%02x.\n", dev->name, phy );
623 TLan_MiiReadReg( dev, phy, i, &data0 );
625 TLan_MiiReadReg( dev, phy, i + 1, &data1 );
627 TLan_MiiReadReg( dev, phy, i + 2, &data2 );
629 TLan_MiiReadReg( dev, phy, i + 3, &data3 );
633 printk( "TLAN: Device %s, Invalid PHY.\n", dev->name );
645 * for which the PHY needs determined.
648 * may also use the internal PHY for part of the functionality.
650 * chip has an internal PHY, and then finds the first external
651 * PHY (starting from address 0) if it exists).
661 u32 phy;
671 priv->phy[0] = TLAN_PHY_MAX_ADDR;
673 priv->phy[0] = TLAN_PHY_NONE;
676 priv->phy[1] = TLAN_PHY_NONE;
677 for ( phy = 0; phy <= TLAN_PHY_MAX_ADDR; phy++ ) {
678 TLan_MiiReadReg( dev, phy, MII_GEN_CTL, &control );
679 TLan_MiiReadReg( dev, phy, MII_GEN_ID_HI, &hi );
680 TLan_MiiReadReg( dev, phy, MII_GEN_ID_LO, &lo );
682 TLAN_DBG( TLAN_DEBUG_GNRL, "PHY found at %02x %04x %04x %04x\n", phy, control, hi, lo );
683 if ( ( priv->phy[1] == TLAN_PHY_NONE ) && ( phy != TLAN_PHY_MAX_ADDR ) ) {
684 priv->phy[1] = phy;
689 if ( priv->phy[1] != TLAN_PHY_NONE ) {
691 } else if ( priv->phy[0] != TLAN_PHY_NONE ) {
694 printk( "TLAN: Cannot initialize device, no PHY was found!\n" );
704 TLAN_DBG( TLAN_DEBUG_GNRL, "%s: Powering down PHY(s).\n", dev->name );
707 TLan_MiiWriteReg( dev, priv->phy[priv->phyNum], MII_GEN_CTL, value );
708 if ( ( priv->phyNum == 0 ) && ( priv->phy[1] != TLAN_PHY_NONE ) && ( ! ( priv->adapter->flags & TLAN_ADAPTER_USE_INTERN_10 ) ) ) {
710 TLan_MiiWriteReg( dev, priv->phy[1], MII_GEN_CTL, value );
726 TLAN_DBG( TLAN_DEBUG_GNRL, "%s: Powering up PHY.\n", dev->name );
729 TLan_MiiWriteReg( dev, priv->phy[priv->phyNum], MII_GEN_CTL, value );
742 u16 phy;
745 phy = priv->phy[priv->phyNum];
747 TLAN_DBG( TLAN_DEBUG_GNRL, "%s: Reseting PHY.\n", dev->name );
750 TLan_MiiWriteReg( dev, phy, MII_GEN_CTL, value );
751 TLan_MiiReadReg( dev, phy, MII_GEN_CTL, &value );
753 TLan_MiiReadReg( dev, phy, MII_GEN_CTL, &value );
770 u16 phy;
774 phy = priv->phy[priv->phyNum];
776 TLan_MiiReadReg( dev, phy, MII_GEN_STS, &status );
777 TLan_MiiReadReg( dev, phy, MII_GEN_STS, &ability );
784 TLan_MiiWriteReg( dev, phy, MII_GEN_CTL, 0x0000);
788 TLan_MiiWriteReg( dev, phy, MII_GEN_CTL, 0x0100);
791 TLan_MiiWriteReg( dev, phy, MII_GEN_CTL, 0x2000);
795 TLan_MiiWriteReg( dev, phy, MII_GEN_CTL, 0x2100);
799 TLan_MiiWriteReg( dev, phy, MII_AN_ADV, (ability << 5) | 1);
801 TLan_MiiWriteReg( dev, phy, MII_GEN_CTL, 0x1000 );
803 TLan_MiiWriteReg( dev, phy, MII_GEN_CTL, 0x1200 );
823 TLan_MiiReadReg( dev, phy, TLAN_TLPHY_CTL, &tctl );
836 TLan_MiiWriteReg( dev, phy, MII_GEN_CTL, control );
838 TLan_MiiWriteReg( dev, phy, TLAN_TLPHY_CTL, tctl );
855 u16 phy;
858 phy = priv->phy[priv->phyNum];
860 TLan_MiiReadReg( dev, phy, MII_GEN_STS, &status );
862 TLan_MiiReadReg( dev, phy, MII_GEN_STS, &status );
879 TLan_MiiReadReg( dev, phy, MII_AN_ADV, &an_adv );
880 TLan_MiiReadReg( dev, phy, MII_AN_LPA, &an_lpa );
898 TLan_MiiWriteReg( dev, phy, MII_GEN_CTL, MII_GC_AUTOENB | MII_GC_DUPLEX );
899 printk( "TLAN: Starting internal PHY with FULL-DUPLEX\n" );
901 TLan_MiiWriteReg( dev, phy, MII_GEN_CTL, MII_GC_AUTOENB );
902 printk( "TLAN: Starting internal PHY with HALF-DUPLEX\n" );
925 * This function monitors PHY condition by reading the status
935 u16 phy;
938 phy = priv->phy[priv->phyNum];
940 /* Get PHY status register */
941 TLan_MiiReadReg( dev, phy, MII_GEN_STS, &phy_status );
989 * phy The address of the PHY to be queried.
996 * of a given register on a PHY. It sends the appropriate info
1002 int TLan_MiiReadReg( struct net_device *dev, u16 phy, u16 reg, u16 *val )
1027 TLan_MiiSendData( dev->base_addr, phy, 5 ); /* Device # */
1077 * dev The address of the PHY to be queried.
1150 * phy The address of the PHY to be written to.
1156 * given register on a PHY. It sends the appropriate info and then
1162 void TLan_MiiWriteReg( struct net_device *dev, u16 phy, u16 reg, u16 val )
1183 TLan_MiiSendData( dev->base_addr, phy, 5 ); /* Device # */
1368 u32 phy[2];
1570 * reports PHY information when used with Donald
1589 * - Added routine to monitor PHY status.
1613 * 10Base-T PHY. This is untestet as I haven't got
2381 u32 phy = priv->phy[priv->phyNum];
2387 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
2389 data->phy_id = phy;
2391 case SIOCGMIIREG: /* Read MII PHY register. */
2397 case SIOCSMIIREG: /* Write MII PHY register. */
2465 TLAN_DBG( TLAN_DEBUG_TX, "TRANSMIT: %s PHY is not ready\n", dev->name );
3084 * and services the PHY.
3094 u32 phy;
3113 phy = priv->phy[priv->phyNum];
3121 TLan_MiiReadReg( dev, phy, TLAN_TLPHY_STS, &tlphy_sts );
3122 TLan_MiiReadReg( dev, phy, TLAN_TLPHY_CTL, &tlphy_ctl );
3125 TLan_MiiWriteReg( dev, phy, TLAN_TLPHY_CTL, tlphy_ctl);
3128 TLan_MiiWriteReg( dev, phy, TLAN_TLPHY_CTL, tlphy_ctl);
3206 * PHY.
3616 u32 phy;
3625 phy = priv->phy[priv->phyNum];
3638 TLan_MiiReadReg( dev, phy, MII_GEN_ID_HI, &tlphy_id1 );
3639 TLan_MiiReadReg( dev, phy, MII_GEN_ID_LO, &tlphy_id2 );
3645 TLan_MiiReadReg( dev, phy, MII_GEN_STS, &status );
3647 TLan_MiiReadReg( dev, phy, MII_GEN_STS, &status );
3648 if ( (status & MII_GS_LINK) && /* We only support link info on Nat.Sem. PHY's */
3651 TLan_MiiReadReg( dev, phy, MII_AN_LPA, &partner );
3652 TLan_MiiReadReg( dev, phy, TLAN_TLPHY_PAR, &tlphy_par );
3684 TLan_MiiReadReg( dev, phy, TLAN_TLPHY_CTL, &tlphy_ctl );
3686 TLan_MiiWriteReg( dev, phy, TLAN_TLPHY_CTL, tlphy_ctl );
