Lines Matching refs:x1
400 #define BRIDGE_REV_A 0x1
409 #define BRIDGE_STAT_FLASH_SELECT (0x1 << 6)
410 #define BRIDGE_STAT_PCI_GIO_N (0x1 << 5)
415 #define BRIDGE_CTRL_EN_CLK50 (0x1 << 30)
416 #define BRIDGE_CTRL_EN_CLK40 (0x1 << 29)
417 #define BRIDGE_CTRL_EN_CLK33 (0x1 << 28)
420 #define BRIDGE_CTRL_RST_PIN(x) (BRIDGE_CTRL_RST(0x1 << (x)))
421 #define BRIDGE_CTRL_IO_SWAP (0x1 << 23)
422 #define BRIDGE_CTRL_MEM_SWAP (0x1 << 22)
423 #define BRIDGE_CTRL_PAGE_SIZE (0x1 << 21)
424 #define BRIDGE_CTRL_SS_PAR_BAD (0x1 << 20)
425 #define BRIDGE_CTRL_SS_PAR_EN (0x1 << 19)
430 #define BRIDGE_CTRL_SSRAM_64K (BRIDGE_CTRL_SSRAM_SIZE(0x1))
432 #define BRIDGE_CTRL_F_BAD_PKT (0x1 << 16)
435 #define BRIDGE_CTRL_CLR_RLLP_CNT (0x1 << 11)
436 #define BRIDGE_CTRL_CLR_TLLP_CNT (0x1 << 10)
437 #define BRIDGE_CTRL_SYS_END (0x1 << 9)
461 #define BRIDGE_DIRMAP_RMF_64 (0x1 << 18)
462 #define BRIDGE_DIRMAP_ADD512 (0x1 << 17)
488 #define BRIDGE_ISR_PMU_ESIZE_FAULT (0x1 << 30)
489 #define BRIDGE_ISR_UNEXP_RESP (0x1 << 29)
490 #define BRIDGE_ISR_BAD_XRESP_PKT (0x1 << 28)
491 #define BRIDGE_ISR_BAD_XREQ_PKT (0x1 << 27)
492 #define BRIDGE_ISR_RESP_XTLK_ERR (0x1 << 26)
493 #define BRIDGE_ISR_REQ_XTLK_ERR (0x1 << 25)
494 #define BRIDGE_ISR_INVLD_ADDR (0x1 << 24)
495 #define BRIDGE_ISR_UNSUPPORTED_XOP (0x1 << 23)
496 #define BRIDGE_ISR_XREQ_FIFO_OFLOW (0x1 << 22)
497 #define BRIDGE_ISR_LLP_REC_SNERR (0x1 << 21)
498 #define BRIDGE_ISR_LLP_REC_CBERR (0x1 << 20)
499 #define BRIDGE_ISR_LLP_RCTY (0x1 << 19)
500 #define BRIDGE_ISR_LLP_TX_RETRY (0x1 << 18)
501 #define BRIDGE_ISR_LLP_TCTY (0x1 << 17)
502 #define BRIDGE_ISR_SSRAM_PERR (0x1 << 16)
503 #define BRIDGE_ISR_PCI_ABORT (0x1 << 15)
504 #define BRIDGE_ISR_PCI_PARITY (0x1 << 14)
505 #define BRIDGE_ISR_PCI_SERR (0x1 << 13)
506 #define BRIDGE_ISR_PCI_PERR (0x1 << 12)
507 #define BRIDGE_ISR_PCI_MST_TIMEOUT (0x1 << 11)
509 #define BRIDGE_ISR_PCI_RETRY_CNT (0x1 << 10)
510 #define BRIDGE_ISR_XREAD_REQ_TIMEOUT (0x1 << 9)
511 #define BRIDGE_ISR_GIO_B_ENBL_ERR (0x1 << 8)
513 #define BRIDGE_ISR_INT(x) (0x1 << (x))
580 #define BRIDGE_IRR_MULTI_CLR (0x1 << 6)
581 #define BRIDGE_IRR_CRP_GRP_CLR (0x1 << 5)
582 #define BRIDGE_IRR_RESP_BUF_GRP_CLR (0x1 << 4)
583 #define BRIDGE_IRR_REQ_DSP_GRP_CLR (0x1 << 3)
584 #define BRIDGE_IRR_LLP_GRP_CLR (0x1 << 2)
585 #define BRIDGE_IRR_SSRAM_GRP_CLR (0x1 << 1)
586 #define BRIDGE_IRR_PCI_GRP_CLR (0x1 << 0)
587 #define BRIDGE_IRR_GIO_GRP_CLR (0x1 << 0)
680 #define BRIDGE_ERRUPPR_DEVMASTER (0x1 << 20) /* Device was master */
681 #define BRIDGE_ERRUPPR_PCIVDEV (0x1 << 19) /* Virtual Req value */
688 #define BRIDGE_INTMODE_CLR_PKT_EN(x) (0x1 << (x))
