Lines Matching refs:VirtReg
135 LiveRangeStage getStage(const LiveInterval &VirtReg) const {
136 return ExtraRegInfo[VirtReg.reg].Stage;
139 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) {
141 ExtraRegInfo[VirtReg.reg].Stage = Stage;
352 bool RAGreedy::LRE_CanEraseVirtReg(unsigned VirtReg) {
353 if (VRM->hasPhys(VirtReg)) {
354 Matrix->unassign(LIS->getInterval(VirtReg));
357 // Unassigned virtreg is probably in the priority queue.
362 void RAGreedy::LRE_WillShrinkVirtReg(unsigned VirtReg) {
363 if (!VRM->hasPhys(VirtReg))
367 LiveInterval &LI = LIS->getInterval(VirtReg);
435 /// tryAssign - Try to assign VirtReg to an available register.
436 unsigned RAGreedy::tryAssign(LiveInterval &VirtReg,
442 if (!Matrix->checkInterference(VirtReg, PhysReg))
451 if (unsigned Hint = MRI->getSimpleHint(VirtReg.reg))
455 if (canEvictInterference(VirtReg, Hint, true, MaxCost)) {
456 evictInterference(VirtReg, Hint, NewVRegs);
470 unsigned CheapReg = tryEvict(VirtReg, Order, NewVRegs, Cost);
504 /// canEvictInterference - Return true if all interferences between VirtReg and
507 /// @param VirtReg Live range that is about to be assigned.
509 /// @param IsHint True when PhysReg is VirtReg's preferred register.
513 bool RAGreedy::canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg,
516 if (Matrix->checkInterference(VirtReg, PhysReg) > LiveRegMatrix::IK_VirtReg)
519 // Find VirtReg's cascade number. This will be unassigned if VirtReg was never
526 unsigned Cascade = ExtraRegInfo[VirtReg.reg].Cascade;
532 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
551 bool Urgent = !VirtReg.isSpillable() &&
553 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(VirtReg.reg)) <
573 if (!Urgent && !shouldEvict(VirtReg, IsHint, *Intf, BreaksHint))
581 /// evictInterference - Evict any interferring registers that prevent VirtReg
584 void RAGreedy::evictInterference(LiveInterval &VirtReg, unsigned PhysReg,
586 // Make sure that VirtReg has a cascade number, and assign that cascade
589 unsigned Cascade = ExtraRegInfo[VirtReg.reg].Cascade;
591 Cascade = ExtraRegInfo[VirtReg.reg].Cascade = NextCascade++;
599 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
608 // The same VirtReg may be present in multiple RegUnits. Skip duplicates.
613 VirtReg.isSpillable() < Intf->isSpillable()) &&
622 /// @param VirtReg Currently unassigned virtual register.
624 /// @return Physreg to assign VirtReg, or 0.
625 unsigned RAGreedy::tryEvict(LiveInterval &VirtReg,
640 BestCost.MaxWeight = VirtReg.weight;
643 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg.reg);
673 if (!canEvictInterference(VirtReg, PhysReg, false, BestCost))
687 evictInterference(VirtReg, BestPhys, NewVRegs);
1114 unsigned RAGreedy::tryRegionSplit(LiveInterval &VirtReg, AllocationOrder &Order,
1206 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this);
1249 unsigned RAGreedy::tryBlockSplit(LiveInterval &VirtReg, AllocationOrder &Order,
1251 assert(&SA->getParent() == &VirtReg && "Live range wasn't analyzed");
1252 unsigned Reg = VirtReg.reg;
1254 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this);
1301 RAGreedy::tryInstructionSplit(LiveInterval &VirtReg, AllocationOrder &Order,
1304 if (!RegClassInfo.isProperSubClass(MRI->getRegClass(VirtReg.reg)))
1309 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this);
1338 DebugVars->splitRegister(VirtReg.reg, LREdit.regs());
1378 // We know that VirtReg is a continuous interval from FirstInstr to
1432 /// tryLocalSplit - Try to split VirtReg into smaller intervals inside its only
1435 unsigned RAGreedy::tryLocalSplit(LiveInterval &VirtReg, AllocationOrder &Order,
1459 // If VirtReg is live across any register mask operands, compute a list of
1462 if (Matrix->checkRegMaskInterference(VirtReg)) {
1466 // Constrain to VirtReg's live range.
1507 bool ProgressRequired = getStage(VirtReg) >= RS_Split2;
1524 if (Matrix->checkRegMaskInterference(VirtReg, PhysReg))
1619 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this);
1628 DebugVars->splitRegister(VirtReg.reg, LREdit.regs());
1655 /// trySplit - Try to split VirtReg or one of its interferences, making it
1657 /// @return Physreg when VirtReg may be assigned and/or new NewVRegs.
1658 unsigned RAGreedy::trySplit(LiveInterval &VirtReg, AllocationOrder &Order,
1661 if (getStage(VirtReg) >= RS_Spill)
1665 if (LIS->intervalIsInOneMBB(VirtReg)) {
1667 SA->analyze(&VirtReg);
1668 unsigned PhysReg = tryLocalSplit(VirtReg, Order, NewVRegs);
1671 return tryInstructionSplit(VirtReg, Order, NewVRegs);
1676 SA->analyze(&VirtReg);
1683 // VirtReg has changed, so all cached queries are invalid.
1685 if (unsigned PhysReg = tryAssign(VirtReg, Order, NewVRegs))
1692 if (getStage(VirtReg) < RS_Split2) {
1693 unsigned PhysReg = tryRegionSplit(VirtReg, Order, NewVRegs);
1699 return tryBlockSplit(VirtReg, Order, NewVRegs);
1707 unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg,
1710 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo);
1711 if (unsigned PhysReg = tryAssign(VirtReg, Order, NewVRegs))
1714 LiveRangeStage Stage = getStage(VirtReg);
1716 << " Cascade " << ExtraRegInfo[VirtReg.reg].Cascade << '\n');
1722 if (unsigned PhysReg = tryEvict(VirtReg, Order, NewVRegs))
1731 setStage(VirtReg, RS_Split);
1733 NewVRegs.push_back(&VirtReg);
1739 if (Stage >= RS_Done || !VirtReg.isSpillable())
1742 // Try splitting VirtReg or interferences.
1743 unsigned PhysReg = trySplit(VirtReg, Order, NewVRegs);
1747 // Finally spill VirtReg itself.
1749 LiveRangeEdit LRE(&VirtReg, NewVRegs, *MF, *LIS, VRM, this);
