Lines Matching refs:ResultReg
391 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1,
394 if (ResultReg == 0) return false;
397 UpdateValueMap(I, ResultReg);
427 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0,
429 if (ResultReg == 0) return false;
432 UpdateValueMap(I, ResultReg);
438 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
440 if (ResultReg != 0) {
442 UpdateValueMap(I, ResultReg);
455 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
459 if (ResultReg == 0)
465 UpdateValueMap(I, ResultReg);
693 unsigned ResultReg = getRegForValue(ResCI);
694 if (ResultReg == 0)
696 UpdateValueMap(Call, ResultReg);
700 unsigned ResultReg = getRegForValue(Call->getArgOperand(0));
701 if (ResultReg == 0)
703 UpdateValueMap(Call, ResultReg);
746 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
750 if (!ResultReg)
753 UpdateValueMap(I, ResultReg);
785 unsigned ResultReg = 0;
791 ResultReg = createResultReg(DstClass);
793 ResultReg).addReg(Op0);
798 if (!ResultReg)
799 ResultReg = FastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0, Op0IsKill);
801 if (!ResultReg)
804 UpdateValueMap(I, ResultReg);
891 unsigned ResultReg = FastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(),
893 if (ResultReg != 0) {
894 UpdateValueMap(I, ResultReg);
917 ResultReg = FastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(),
919 if (ResultReg == 0)
922 UpdateValueMap(I, ResultReg);
945 unsigned ResultReg;
948 ResultReg = I->second;
950 ResultReg = FuncInfo.InitializeRegForValue(Op0);
961 ResultReg += TLI.getNumRegisters(FuncInfo.Fn->getContext(), AggValueVTs[i]);
963 UpdateValueMap(EVI, ResultReg);
1176 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Op0IsKill, Imm);
1177 if (ResultReg != 0)
1178 return ResultReg;
1198 unsigned ResultReg = createResultReg(RC);
1201 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg);
1202 return ResultReg;
1208 unsigned ResultReg = createResultReg(RC);
1212 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
1218 ResultReg).addReg(II.ImplicitDefs[0]);
1221 return ResultReg;
1228 unsigned ResultReg = createResultReg(RC);
1232 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
1240 ResultReg).addReg(II.ImplicitDefs[0]);
1242 return ResultReg;
1250 unsigned ResultReg = createResultReg(RC);
1254 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
1264 ResultReg).addReg(II.ImplicitDefs[0]);
1266 return ResultReg;
1273 unsigned ResultReg = createResultReg(RC);
1277 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
1285 ResultReg).addReg(II.ImplicitDefs[0]);
1287 return ResultReg;
1294 unsigned ResultReg = createResultReg(RC);
1298 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
1308 ResultReg).addReg(II.ImplicitDefs[0]);
1310 return ResultReg;
1317 unsigned ResultReg = createResultReg(RC);
1321 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
1329 ResultReg).addReg(II.ImplicitDefs[0]);
1331 return ResultReg;
1339 unsigned ResultReg = createResultReg(RC);
1343 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
1353 ResultReg).addReg(II.ImplicitDefs[0]);
1355 return ResultReg;
1363 unsigned ResultReg = createResultReg(RC);
1367 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
1377 ResultReg).addReg(II.ImplicitDefs[0]);
1379 return ResultReg;
1385 unsigned ResultReg = createResultReg(RC);
1389 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg).addImm(Imm);
1393 ResultReg).addReg(II.ImplicitDefs[0]);
1395 return ResultReg;
1401 unsigned ResultReg = createResultReg(RC);
1405 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
1410 ResultReg).addReg(II.ImplicitDefs[0]);
1412 return ResultReg;
1418 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
1424 DL, TII.get(TargetOpcode::COPY), ResultReg)
1426 return ResultReg;
