Lines Matching refs:Rn
458 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
478 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
483 DecodeGPR32RegisterClass(Inst, Rn, Address, Decoder);
552 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
557 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
560 DecodeVPR128RegisterClass(Inst, Rn, Address, Decoder);
576 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
589 // Rn_wb, Rt, Rt2, Rn, Imm
590 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
599 if (Indexed && V == 0 && Rn != 31 && (Rt == Rn || Rt2 == Rn))
643 // Rt, Rt2, Rn_wb, Rt2, Rn, Imm
644 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
648 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
659 unsigned Rn = fieldFromInstruction(Val, 5, 5);
683 if (!Check(S, DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder)))
739 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
747 // It's a store, the MCInst gets: Rn_wb, Rt, Rn, Imm
748 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
775 // It's a load, the MCInst gets: Rt, Rn_wb, Rn, Imm
776 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
779 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
783 // N.b. The official documentation says undpredictable if Rt == Rn, but this
787 if (V == 0 && Rt == Rn && Rn != 31)
