Home | History | Annotate | Download | only in ARM

Lines Matching refs:UOps

2389     int UOps = ItinData->getNumMicroOps(Desc.getSchedClass());
2390 assert(UOps >= 0 && "bad # UOps");
2391 return UOps;
2657 llvm_unreachable("Unexpected multi-uops instruction!");
2662 // The number of uOps for load / store multiple are determined by the number
2722 int UOps = 1 + NumRegs; // One for address computation, one for each ld / st.
2747 ++UOps; // One for base register writeback.
2752 UOps += 2; // One for base reg wb, one for write to pc.
2755 return UOps;
3613 // For instructions with variable uops, use uops as latency.
4022 // VLD1LNd32 - Writes all D-regs, explicit partial D update, 2 uops.
4023 // VLD1DUPd32 - Writes all D-regs, no partial reg update, 2 uops.
4114 // instruction is micro-coded with 2 uops, so don't do this until we can