Lines Matching refs:RetVT
138 unsigned FastEmitInst_extractsubreg(MVT RetVT,
215 bool FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
476 unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT,
479 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
2041 bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
2051 if (RetVT != MVT::isVoid) {
2054 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg));
2057 if (RVLocs.size() == 2 && RetVT == MVT::f64) {
2078 if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
2204 MVT RetVT;
2206 RetVT = MVT::isVoid;
2207 else if (!isTypeLegal(RetTy, RetVT))
2211 if (RetVT != MVT::isVoid && RetVT != MVT::i32) {
2214 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, false));
2215 if (RVLocs.size() >= 2 && RetVT != MVT::f64)
2282 if (!FinishCall(RetVT
2313 MVT RetVT;
2315 RetVT = MVT::isVoid;
2316 else if (!isTypeLegal(RetTy, RetVT) && RetVT != MVT::i16 &&
2317 RetVT != MVT::i8 && RetVT != MVT::i1)
2321 if (RetVT != MVT::isVoid && RetVT != MVT::i1 && RetVT != MVT::i8 &&
2322 RetVT != MVT::i16 && RetVT != MVT::i32) {
2325 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg));
2326 if (RVLocs.size() >= 2 && RetVT != MVT::f64)
2426 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, isVarArg))
