Lines Matching defs:Const
77 const TargetMachine &TM, SmallVector<CCValAssign, 16> &locs,
89 static const uint16_t GPRArgRegs[] = {
891 std::pair<const TargetRegisterClass*, uint8_t>
892 ARMTargetLowering::findRepresentativeClass(MVT VT) const{
893 const TargetRegisterClass *RRC = 0;
928 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
1068 EVT ARMTargetLowering::getSetCCResultType(EVT VT) const {
1075 const TargetRegisterClass *ARMTargetLowering::getRegClassFor(MVT VT) const {
1091 const TargetLibraryInfo *libInfo) const {
1097 unsigned ARMTargetLowering::getMaximalGlobalOffset() const {
1101 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
1119 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1120 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1191 bool isVarArg) const {
1231 const SmallVectorImpl<ISD::InputArg> &Ins,
1233 SmallVectorImpl<SDValue> &InVals) const {
1304 const CCValAssign &VA,
1305 ISD::ArgFlagsTy Flags) const {
1320 ISD::ArgFlagsTy Flags) const {
1344 SmallVectorImpl<SDValue> &InVals) const {
1466 SDValue Const = DAG.getConstant(4*i, MVT::i32);
1467 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
1552 const GlobalValue *GV = G->getGlobal();
1566 const char *Sym = S->getSymbol();
1582 const GlobalValue *GV = G->getGlobal();
1618 const char *Sym = S->getSymbol();
1675 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
1676 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
1708 CCState *State, unsigned &size, unsigned Align) const {
1745 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
1746 const TargetInstrInfo *TII) {
1793 const SmallVectorImpl<ISD::OutputArg> &Outs,
1794 const SmallVectorImpl<SDValue> &OutVals,
1795 const SmallVectorImpl<ISD::InputArg> &Ins,
1796 SelectionDAG& DAG) const {
1797 const Function *CallerF = DAG.getMachineFunction().getFunction();
1867 const ARMFunctionInfo *AFI_Caller = DAG.getMachineFunction().
1888 const MachineRegisterInfo *MRI = &MF.getRegInfo();
1889 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1929 const SmallVectorImpl<ISD::OutputArg> &Outs,
1930 LLVMContext &Context) const {
1940 const SmallVectorImpl<ISD::OutputArg> &Outs,
1941 const SmallVectorImpl<SDValue> &OutVals,
1942 DebugLoc dl, SelectionDAG &DAG) const {
2026 bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2090 bool ARMTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2121 unsigned ARMTargetLowering::getJumpTableEncoding() const {
2126 SelectionDAG &DAG) const {
2132 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
2158 SelectionDAG &DAG) const {
2200 TLSModel::Model model) const {
2201 const GlobalValue *GV = GA->getGlobal();
2250 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
2270 SelectionDAG &DAG) const {
2273 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2313 SelectionDAG &DAG) const {
2316 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2373 SelectionDAG &DAG) const {
2395 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
2404 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
2412 const ARMSubtarget *Subtarget) const {
2457 const ARMSubtarget *Subtarget) {
2486 const ARMSubtarget *Subtarget) {
2504 const ARMSubtarget *Subtarget) {
2539 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2547 DebugLoc dl) const {
2551 const TargetRegisterClass *RC;
2582 const {
2609 const Value *OrigArg,
2612 bool ForceMutable) const {
2640 const TargetRegisterClass *RC;
2668 const SmallVectorImpl<ISD::InputArg>
2672 const {
2726 const TargetRegisterClass *RC;
2736 (const TargetRegisterClass*)&ARM::tGPRRegClass :
2737 (const TargetRegisterClass*)&ARM::GPRRegClass;
2834 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
2846 DebugLoc dl) const {
2904 DebugLoc dl) const {
2916 ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
2934 SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
2946 const ConstantSDNode *CMOVTrue =
2948 const ConstantSDNode *CMOVFalse =
2986 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
3023 const ARMSubtarget *Subtarget) {
3090 ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
3140 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
3183 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
3316 SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
3398 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
3419 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
3442 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3492 SelectionDAG &DAG) const {
3528 SelectionDAG &DAG) const {
3560 SelectionDAG &DAG) const {
3578 const ARMSubtarget *ST) {
3683 const ARMSubtarget *ST) {
3698 const ARMSubtarget *ST) {
3733 const ARMSubtarget *ST) {
4038 const ARMSubtarget *ST) const {
4337 const ARMSubtarget *ST, DebugLoc dl) {
4356 const ARMSubtarget *ST) const {
4547 SelectionDAG &DAG) const {
4691 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
4692 EVT VT) const {
5123 const EVT &OrigTy,
5124 const EVT &ExtTy,
5208 const APInt &CInt = C->getAPIntValue();
5554 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
5616 SelectionDAG &DAG) const {
5676 unsigned Size) const {
5681 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5687 (const TargetRegisterClass*)&ARM::rGPRRegClass :
5688 (const TargetRegisterClass*)&ARM::GPRRegClass);
5714 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5779 unsigned Size, unsigned BinOpcode) const {
5781 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5783 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5828 const TargetRegisterClass *TRC = isThumb2 ?
5829 (const TargetRegisterClass*)&ARM::rGPRRegClass :
5830 (const TargetRegisterClass*)&ARM::GPRRegClass;
5887 ARMCC::CondCodes Cond) const {
5888 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5890 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5939 const TargetRegisterClass *TRC = isThumb2 ?
5940 (const TargetRegisterClass*)&ARM::rGPRRegClass :
5941 (const TargetRegisterClass*)&ARM::GPRRegClass;
6004 bool IsMinMax, ARMCC::CondCodes CC) const {
6006 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6008 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6047 const TargetRegisterClass *TRC = isThumb2 ?
6048 (const TargetRegisterClass*)&ARM::tGPRRegClass :
6049 (const TargetRegisterClass*)&ARM::GPRRegClass;
6176 MachineBasicBlock *DispatchBB, int FI) const {
6177 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6183 const Function *F = MF->getFunction();
6194 const TargetRegisterClass *TRC = isThumb ?
6195 (const TargetRegisterClass*)&ARM::tGPRRegClass :
6196 (const TargetRegisterClass*)&ARM::GPRRegClass;
6291 EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const {
6292 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6300 const TargetRegisterClass *TRC = Subtarget->isThumb() ?
6301 (const TargetRegisterClass*)&ARM::tGPRRegClass :
6302 (const TargetRegisterClass*)&ARM::GPRnopcRegClass;
6392 const ARMBaseInstrInfo *AII = static_cast<const ARMBaseInstrInfo*>(TII);
6393 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo();
6466 const Constant *C = ConstantInt::get(Int32Ty, NumLPads);
6558 const Constant *C = ConstantInt::get(Int32Ty, NumLPads);
6626 const uint16_t *SavedRegs = RI.getCalleeSavedRegs(MF);
6704 EmitStructByval(MachineInstr *MI, MachineBasicBlock *BB) const {
6708 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6709 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6724 const TargetRegisterClass *TRC = isThumb2 ?
6725 (const TargetRegisterClass*)&ARM::tGPRRegClass :
6726 (const TargetRegisterClass*)&ARM::GPRRegClass;
6727 const TargetRegisterClass *TRC_Vec = 0;
6747 TRC_Vec = (const TargetRegisterClass*)&ARM::DPairRegClass;
6753 TRC_Vec = (const TargetRegisterClass*)&ARM::DPRRegClass;
6887 const Constant *C = ConstantInt::get(Int32Ty, LoopSize);
7006 MachineBasicBlock *BB) const {
7007 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7195 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7312 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7328 (const TargetRegisterClass*)&ARM::rGPRRegClass :
7329 (const TargetRegisterClass*)&ARM::GPRRegClass);
7381 SDNode *Node) const {
7388 const MCInstrDesc *MCID = &MI->getDesc();
7399 const ARMBaseInstrInfo *TII =
7400 static_cast<const ARMBaseInstrInfo*>(getTargetMachine().getInstrInfo());
7425 const MachineOperand &MO = MI->getOperand(i);
7595 const ARMSubtarget *Subtarget) {
7654 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7689 const ARMSubtarget *Subtarget) {
7822 const ARMSubtarget *Subtarget) {
7834 const ARMSubtarget *Subtarget){
7853 const ARMSubtarget *Subtarget) {
7892 const ARMSubtarget *Subtarget) {
7920 const ARMSubtarget *Subtarget) {
8004 const ARMSubtarget *Subtarget) {
8048 const ARMSubtarget *Subtarget) {
8238 const ARMSubtarget *Subtarget) {
8353 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8577 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8886 const ARMSubtarget *Subtarget) {
8922 const ARMSubtarget *Subtarget) {
9162 const ARMSubtarget *ST) {
9178 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9209 const ARMSubtarget *ST) {
9221 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9249 const ARMSubtarget *ST) {
9333 ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const {
9396 DAGCombinerInfo &DCI) const {
9456 EVT VT) const {
9460 bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
9503 MachineFunction &MF) const {
9504 const Function *F = MF.getFunction();
9533 bool ARMTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
9582 const ARMSubtarget *Subtarget) {
9615 const ARMSubtarget *Subtarget) {
9651 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
9652 EVT VT) const {
9686 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
9687 Type *Ty) const {
9749 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
9763 bool ARMTargetLowering::isLegalAddImmediate(int64_t Imm) const {
9865 SelectionDAG &DAG) const {
9904 SelectionDAG &DAG) const {
9948 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
9951 const SelectionDAG &DAG,
9952 unsigned Depth) const {
9974 bool ARMTargetLowering::ExpandInlineAsm(CallInst *CI) const {
10008 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
10037 AsmOperandInfo &info, const char *constraint) const {
10066 typedef std::pair<unsigned, const TargetRegisterClass*> RCPair;
10068 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
10069 EVT VT) const {
10116 SelectionDAG &DAG) const {
10279 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
10302 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
10316 const CallInst &I,
10317 unsigned Intrinsic) const {
