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Lines Matching refs:getDefRegState

353     MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef)
778     .addReg(Base, getDefRegState(true)) // WB base register
931       .addReg(Base, getDefRegState(true)) // WB base register
934       .addReg(MO.getReg(), (isLd ? getDefRegState(true) :
1084       .addReg(Reg, getDefRegState(true) | getDeadRegState(RegDeadKill))
1142           .addReg(EvenReg, getDefRegState(isLd) | getDeadRegState(EvenDeadKill))
1143           .addReg(OddReg,  getDefRegState(isLd) | getDeadRegState(OddDeadKill));