Lines Matching defs:newOpc
6829 unsigned NewOpc;
6832 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
6833 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
6834 case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
6838 TmpInst.setOpcode(NewOpc);
6865 unsigned newOpc;
6868 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
6869 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
6870 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
6871 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break;
6873 TmpInst.setOpcode(newOpc);
6899 unsigned newOpc;
6902 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
6903 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
6904 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
6905 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
6906 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
6910 TmpInst.setOpcode(newOpc);
6916 if (newOpc != ARM::t2RRX)
7303 unsigned NewOpc;
7306 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
7307 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
7308 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
7309 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
7313 TmpInst.setOpcode(NewOpc);
7348 unsigned newOpc;
7353 case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
7354 case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
7355 case ARM::EORrsi: newOpc = ARM::EORrr; break;
7356 case ARM::BICrsi: newOpc = ARM::BICrr; break;
7357 case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
7358 case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
7365 TmpInst.setOpcode(newOpc);
7418 unsigned NewOpc;
7421 case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
7422 case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
7423 case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
7424 case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
7425 case ARM::t2RORrr: NewOpc = ARM::tROR; break;
7426 case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
7429 TmpInst.setOpcode(NewOpc);
7457 unsigned NewOpc;
7460 case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
7461 case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
7462 case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
7463 case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
7466 TmpInst.setOpcode(NewOpc);
