Lines Matching refs:RegNum
353 unsigned RegNum;
358 unsigned RegNum;
387 unsigned RegNum;
543 return Reg.RegNum;
1172 .contains(VectorList.RegNum));
1188 .contains(VectorList.RegNum));
1215 .contains(VectorList.RegNum));
1442 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1443 Inst.addOperand(MCOperand::CreateReg(RegNum));
1779 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1975 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1981 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2002 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2007 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2142 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
2144 Op->Reg.RegNum = RegNum;
2159 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
2161 Op->Reg.RegNum = RegNum;
2244 static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count,
2247 Op->VectorList.RegNum = RegNum;
2255 static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count,
2259 Op->VectorList.RegNum = RegNum;
2267 static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count,
2272 Op->VectorList.RegNum = RegNum;
2319 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
2324 Op->PostIdxReg.RegNum = RegNum;
2402 << PostIdxReg.RegNum;
2460 << VectorList.RegNum << ">";
2464 << VectorList.RegNum << ">";
2468 << VectorList.Count << " * " << VectorList.RegNum << ">";
2504 unsigned RegNum = MatchRegisterName(lowerCase);
2505 if (!RegNum) {
2506 RegNum = StringSwitch<unsigned>(lowerCase)
2529 if (!RegNum) {
2543 return RegNum;
