Lines Matching refs:ShiftReg
401 unsigned ShiftReg;
1486 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
2169 unsigned ShiftReg,
2175 Op->RegShiftedReg.ShiftReg = ShiftReg;
2428 << " " << RegShiftedReg.ShiftReg << ">";
2582 int ShiftReg = 0;
2587 ShiftReg = SrcReg;
2622 ShiftReg = tryParseRegister();
2623 if (ShiftReg == -1) {
2634 if (ShiftReg && ShiftTy != ARM_AM::rrx)
2636 ShiftReg, Imm,
