Lines Matching refs:addReg
121 .addReg(SrcReg, getKillRegState(KillSrc)));
143 .addReg(SrcReg, getKillRegState(isKill))
195 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
200 .addReg(DestReg)
202 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
209 .addReg(BaseReg, RegState::Kill)
210 .addReg(DestReg, RegState::Kill)
211 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
215 .addReg(DestReg, RegState::Kill)
216 .addReg(BaseReg, RegState::Kill)
217 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
230 .addReg(BaseReg).setMIFlags(MIFlags));
242 .addReg(BaseReg).addImm(ThisVal/4).setMIFlags(MIFlags));
281 .addReg(BaseReg, RegState::Kill)
