Lines Matching refs:BuildMI
1134 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
1138 BuildMI(BB, DL, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr);
1139 BuildMI(BB, DL, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes);
1142 BuildMI(BB, DL, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr);
1146 BuildMI(BB, DL, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0);
1147 BuildMI(BB, DL, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB);
1225 BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2)
1227 BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr)
1229 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1230 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1231 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1233 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1235 BuildMI
1236 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(ShiftAmt).addReg(Incr);
1258 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
1263 BuildMI(BB, DL, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2);
1264 BuildMI(BB, DL, TII->get(Mips::NOR), BinOpRes)
1266 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1270 BuildMI(BB, DL, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2);
1271 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1274 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask);
1277 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
1279 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
1281 BuildMI(BB, DL, TII->get(SC), Success)
1283 BuildMI(BB, DL, TII->get(Mips::BEQ))
1294 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
1296 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
1298 BuildMI(BB, DL, TII->get(Mips::SLL), SllRes)
1300 BuildMI(BB, DL, TII->get(Mips::SRA), Dest)
1372 BuildMI(BB, DL, TII->get(LL), Dest).addReg(Ptr).addImm(0);
1373 BuildMI(BB, DL, TII->get(BNE))
1380 BuildMI(BB, DL, TII->get(SC), Success)
1382 BuildMI(BB, DL, TII->get(BEQ))
1468 BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2)
1470 BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr)
1472 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1473 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1474 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1476 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1478 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1479 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal)
1481 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal)
1483 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal)
1485 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal)
1493 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
1494 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
1496 BuildMI(BB, DL, TII->get(Mips::BNE))
1505 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
1507 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
1509 BuildMI(BB, DL, TII->get(SC), Success)
1511 BuildMI(BB, DL, TII->get(Mips::BEQ))
1521 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
1523 BuildMI(BB, DL, TII->get(Mips::SLL), SllRes)
1525 BuildMI(BB, DL, TII->get(Mips::SRA), Dest)
