Lines Matching refs:ShiftAmt
1175 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1218 // sll shiftamt,ptrlsb2,3
1220 // sll mask,maskupper,shiftamt
1222 // sll incr2,incr,shiftamt
1230 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1234 .addReg(ShiftAmt).addReg(MaskUpper);
1236 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(ShiftAmt).addReg(Incr);
1288 // srl srlres,maskedoldval1,shiftamt
1297 .addReg(ShiftAmt).addReg(MaskedOldVal1);
1411 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1459 // sll shiftamt,ptrlsb2,3
1461 // sll mask,maskupper,shiftamt
1464 // sll shiftedcmpval,maskedcmpval,shiftamt
1466 // sll shiftednewval,maskednewval,shiftamt
1473 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1477 .addReg(ShiftAmt).addReg(MaskUpper);
1482 .addReg(ShiftAmt).addReg(MaskedCmpVal);
1486 .addReg(ShiftAmt).addReg(MaskedNewVal);
1515 // srl srlres,maskedoldval0,shiftamt
1522 .addReg(ShiftAmt).addReg(MaskedOldVal0);