Lines Matching defs:Const
35 const R600RegisterInfo &R600InstrInfo::getRegisterInfo() const {
39 bool R600InstrInfo::isTrig(const MachineInstr &MI) const {
43 bool R600InstrInfo::isVector(const MachineInstr &MI) const {
51 bool KillSrc) const {
76 unsigned DstReg, int64_t Imm) const {
87 unsigned R600InstrInfo::getIEQOpcode() const {
91 bool R600InstrInfo::isMov(unsigned Opcode) const {
106 bool R600InstrInfo::isPlaceHolderOpcode(unsigned Opcode) const {
114 bool R600InstrInfo::isReductionOp(unsigned Opcode) const {
123 bool R600InstrInfo::isCubeOp(unsigned Opcode) const {
134 bool R600InstrInfo::isALUInstr(unsigned Opcode) const {
143 R600InstrInfo::fitsConstReadLimitations(const std::vector<unsigned> &Consts)
144 const {
168 R600InstrInfo::canBundle(const std::vector<MachineInstr *> &MIs) const {
171 const MachineInstr *MI = MIs[i];
173 const R600Operands::Ops OpTable[3][2] = {
187 unsigned Const = MI->getOperand(
189 Consts.push_back(Const);
196 DFAPacketizer *R600InstrInfo::CreateTargetScheduleState(const TargetMachine *TM,
197 const ScheduleDAG *DAG) const {
198 const InstrItineraryData *II = TM->getInstrItineraryData();
235 bool AllowModify) const {
298 int R600InstrInfo::getBranchInstr(const MachineOperand &op) const {
299 const MachineInstr *MI = op.getParent();
312 const SmallVectorImpl<MachineOperand> &Cond,
313 DebugLoc DL) const {
345 R600InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
393 R600InstrInfo::isPredicated(const MachineInstr *MI) const {
409 R600InstrInfo::isPredicable(MachineInstr *MI) const {
429 const BranchProbability &Probability) const{
440 const BranchProbability &Probability) const {
447 const BranchProbability &Probability)
448 const {
454 MachineBasicBlock &FMBB) const {
460 R600InstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
495 std::vector<MachineOperand> &Pred) const {
501 R600InstrInfo::SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
502 const SmallVectorImpl<MachineOperand> &Pred2) const {
509 const SmallVectorImpl<MachineOperand> &Pred) const {
523 unsigned int R600InstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
524 const MachineInstr *MI,
525 unsigned *PredCost) const {
531 int R600InstrInfo::getIndirectIndexBegin(const MachineFunction &MF) const {
532 const MachineRegisterInfo &MRI = MF.getRegInfo();
533 const MachineFrameInfo *MFI = MF.getFrameInfo();
554 int R600InstrInfo::getIndirectIndexEnd(const MachineFunction &MF) const {
556 const MachineFrameInfo *MFI = MF.getFrameInfo();
571 const MachineFunction &MF) const {
572 const AMDGPUFrameLowering *TFL =
573 static_cast<const AMDGPUFrameLowering*>(TM.getFrameLowering());
595 unsigned Channel) const {
601 const TargetRegisterClass * R600InstrInfo::getIndirectAddrStoreRegClass(
602 unsigned SourceReg) const {
606 const TargetRegisterClass *R600InstrInfo::getIndirectAddrLoadRegClass() const {
613 unsigned OffsetReg) const {
629 unsigned OffsetReg) const {
644 const TargetRegisterClass *R600InstrInfo::getSuperIndirectRegClass() const {
654 unsigned Src1Reg) const {
692 uint64_t Imm) const {
699 int R600InstrInfo::getOperandIdx(const MachineInstr &MI,
700 R600Operands::Ops Op) const {
705 R600Operands::Ops Op) const {
735 int64_t Imm) const {
746 bool R600InstrInfo::hasFlagOperand(const MachineInstr &MI) const {
751 unsigned Flag) const {
806 unsigned Flag) const {
827 unsigned Flag) const {
