Lines Matching refs:v4f32
866 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
868 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
869 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
870 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
871 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
872 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
873 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
874 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
875 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
876 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
877 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
878 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
879 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
920 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1004 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1005 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1006 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1007 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1008 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1022 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
1031 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1036 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1122 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1128 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1165 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1450 return MVT::v4f32;
1548 case MVT::v4f32: case MVT::v2f64:
1667 // If we don't have SSE2 available, convert to v4f32 so the generated
1670 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2183 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
3334 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
4409 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4504 // represented by v4f32 and then be manipulated by target suported shuffles.
4528 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4530 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5647 // Next, we iteratively mix elements, e.g. for v4f32:
6184 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
6198 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
6231 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
6554 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
6556 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
6557 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
6558 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
6567 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6573 // v4i32 or v4f32
6595 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
6755 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
6852 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
6857 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
6860 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
6888 if (VT == MVT::v4i32 || VT == MVT::v4f32)
7290 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
8612 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
8733 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
11619 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
12279 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
12285 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
17083 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
17098 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
18231 case MVT::v4f32:
