Lines Matching full:imul
113 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", [],
117 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", [],
121 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", [],
125 def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src), "imul{q}\t$src", [],
132 "imul{b}\t$src", [], IIC_IMUL8>, SchedLoadReg<WriteIMulLd>;
136 "imul{w}\t$src", [], IIC_IMUL16_MEM>, OpSize,
141 "imul{l}\t$src", [], IIC_IMUL32_MEM>, SchedLoadReg<WriteIMulLd>;
145 "imul{q}\t$src", [], IIC_IMUL64>, SchedLoadReg<WriteIMulLd>;
154 // X = IMUL Y, Z --> X = IMUL Z, Y
157 "imul{w}\t{$src2, $dst|$dst, $src2}",
162 "imul{l}\t{$src2, $dst|$dst, $src2}",
168 "imul{q}\t{$src2, $dst|$dst, $src2}",
178 "imul{w}\t{$src2, $dst|$dst, $src2}",
185 "imul{l}\t{$src2, $dst|$dst, $src2}",
192 "imul{q}\t{$src2, $dst|$dst, $src2}",
208 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
214 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
221 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
227 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
233 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
239 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
249 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
256 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
263 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
269 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
276 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
283 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
