Lines Matching full:cycles
2 {0x0, CTR(0) | CTR(1) | CTR(2) | CTR(3), 0, "CYCLES",
3 "0-0 Cycles"},
9 "3-0 Stall cycles due to register indirect jumps (including non-predicted JR $31), ERET/WAIT instructions, and IFU determined exception"},
15 "7-0 Instruction cache miss stall cycles"},
17 "8-0 Uncached instruction fetch stall cycles"},
21 "11-0 Cycles IFU-IDU gate is closed (to prevent upstream from getting ahead) due to mispredicted branch"},
23 "12-0 Cycles IFU-IDU gate is closed (waiting for downstream to unclog) due to MTC0/MFC0 sequence in pipe, EHB, or blocked DD, DR, or DS"},
25 "13-0 DR stage stall cycles due to DDQ0 (ALU out-of-order dispatch queue) full"},
27 "14-0 DR stage stall cycles due to ALCB (ALU completion buffers) full"},
29 "15-0 DR stage stall cycles due to CLDQ (data comming back from FPU) full"},
31 "16-0 DDQ0 (ALU out-of-order dispatch queue) empty cycles"},
33 "17-0 DDQ0 (ALU out-of-order dispatch queue) no issue cycles with valid instructions but operands not ready"},
35 "18-0 DDQ0 (ALU out-of-order dispatch queue) no issue cycles with valid instructions due to operand(s) not available, MDU busy, or CorExt resource busy"},
39 "20-0 Either DDQ0 (ALU out-of-order dispatch queue) or DDQ1 (AGEN out-of-order dispatch queue) valid instruction issue cycles"},
41 "21-0 Out-of-order ALU issue cycles (issued instruction is not the oldest in the pool)"},
53 "27-0 Load/store graduation blocked cycles due to CP1/2 store data not ready, SYNC/SYNCI/SC/CACHEOP at the head, or FSB/LDQ/WBB/ITU FIFO full"},
59 "30-0 Pipe stall cycles due to FSB full"},
61 "31-0 Pipe stall cycles due to LDQ full"},
63 "32-0 Pipe stall cycles due to WBB full"},
97 "53-0 No instructions graduated cycles"},
99 "54-0 One instruction graduated cycles"},
101 "55-0 GFIFO blocked cycles"},
103 "56-0 Cycles from the time of a pipe kill due to mispredict until the first new instruction graduates"},
105 "57-0 Mispredicted branch instruction graduation cycles without the delay slot"},
149 "11-1 Cycles IFU-IDU gate open but no instructions fetched by IFU"},
151 "13-1 DR stage stall cycles due to DDQ1 (AGEN out-of-order dispatch queue) full"},
153 "14-1 DR stage stall cycles due to AGCB (AGEN completion buffers) full"},
155 "15-1 DR stage stall cycles due to IODQ (data comming back from IO) full"},
157 "16-1 DDQ1 (AGEN out-of-order dispatch queue) empty cycles"},
159 "17-1 DDQ1 (AGEN out-of-order dispatch queue) no issue cycles with valid instructions but operands not ready"},
161 "18-1 DDQ1 (AGEN out-of-order dispatch queue) no issue cycles with valid instructions due to operand(s) not available, non-issued stores blocking ready to issue loads, or non-issued CACHEOPs blocking ready to issue loads"},
165 "20-1 Both DDQ0 (ALU out-of-order dispatch queue) and DDQ1 (AGEN out-of-order dispatch queue) valid instruction issue cycles"},
167 "21-1 Out-of-order AGEN issue cycles (issued instruction is not the oldest in the pool)"},
183 "29-1 Cycles a L2 miss is outstanding, but not necessarily stalling the pipeline"},
221 "54-1 Two instructions graduated cycles"},
