Lines Matching full:active_tc
146 return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0];
151 env->active_tc.LO[0] = (int32_t)HILO;
152 env->active_tc.HI[0] = (int32_t)(HILO >> 32);
157 env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
158 arg1 = env->active_tc.HI[0] = (int32_t)(HILO >> 32);
163 arg1 = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
164 env->active_tc.HI[0] = (int32_t)(HILO >> 32);
269 muls64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2);
274 mulu64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2);
592 return env->active_tc.CP0_TCStatus;
600 return env->active_tc.CP0_TCStatus;
607 return env->active_tc.CP0_TCBind;
615 return env->active_tc.CP0_TCBind;
622 return env->active_tc.PC;
630 return env->active_tc.PC;
637 return env->active_tc.CP0_TCHalt;
645 return env->active_tc.CP0_TCHalt;
652 return env->active_tc.CP0_TCContext;
660 return env->active_tc.CP0_TCContext;
667 return env->active_tc.CP0_TCSchedule;
675 return env->active_tc.CP0_TCSchedule;
682 return env->active_tc.CP0_TCScheFBack;
690 return env->active_tc.CP0_TCScheFBack;
706 tcstatus = env->active_tc.CP0_TCStatus;
720 tcstatus = env->active_tc.CP0_TCStatus;
762 tcstatus = env->active_tc.CP0_Debug_tcstatus;
774 return env->active_tc.PC;
779 return env->active_tc.CP0_TCHalt;
784 return env->active_tc.CP0_TCContext;
789 return env->active_tc.CP0_TCSchedule;
794 return env->active_tc.CP0_TCScheFBack;
912 newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
916 env->active_tc.CP0_TCStatus = newval;
926 env->active_tc.CP0_TCStatus = arg1;
938 newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
939 env->active_tc.CP0_TCBind = newval;
951 newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
952 env->active_tc.CP0_TCBind = newval;
961 env->active_tc.PC = arg1;
962 env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
972 env->active_tc.PC = arg1;
973 env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
986 env->active_tc.CP0_TCHalt = arg1 & 0x1;
998 env->active_tc.CP0_TCHalt = arg1;
1005 env->active_tc.CP0_TCContext = arg1;
1013 env->active_tc.CP0_TCContext = arg1;
1020 env->active_tc.CP0_TCSchedule = arg1;
1028 env->active_tc.CP0_TCSchedule = arg1;
1035 env->active_tc.CP0_TCScheFBack = arg1;
1043 env->active_tc.CP0_TCScheFBack = arg1;
1126 uint32_t tcst = env->active_tc.CP0_TCStatus & ~0xff;
1127 env->active_tc.CP0_TCStatus = tcst | (val & 0xff);
1141 tcstatus = (env->active_tc.CP0_TCStatus & ~0xff) | (arg1 & 0xff);
1142 env->active_tc.CP0_TCStatus = tcstatus;
1188 env->active_tc.CP0_TCStatus = tcstatus;
1294 env->active_tc.CP0_Debug_tcstatus = val;
1332 return env->active_tc.gpr[sel];
1342 return env->active_tc.LO[sel];
1352 return env->active_tc.HI[sel];
1362 return env->active_tc.ACX[sel];
1372 return env->active_tc.DSPControl;
1382 env->active_tc.gpr[sel] = arg1;
1392 env->active_tc.LO[sel] = arg1;
1402 env->active_tc.HI[sel] = arg1;
1412 env->active_tc.ACX[sel] = arg1;
1422 env->active_tc.DSPControl = arg1;
1478 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
1752 env->active_tc.PC, env->CP0_EPC);
1765 env->active_tc.PC, env->CP0_EPC);
1783 env->active_tc.PC = env->CP0_ErrorEPC;
1786 env->active_tc.PC = env->CP0_EPC;
1797 env->active_tc.PC = env->CP0_DEPC;
1854 if (env->active_tc.gpr[4] == 0)
1855 env->active_tc.gpr[2] = -1;
1858 env->active_tc.gpr[2] = -1;
1862 printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
1868 unsigned char *fmt = (void *)(unsigned long)env->active_tc.gpr[4];
