Lines Matching refs:destination
72 // the same as the destination, the destination is ignored and
94 // Clear this move's destination to indicate a pending move. The actual
95 // destination is saved in a stack-allocated local. Recursion may allow
98 LOperand* destination = moves_[index].destination();
103 // as this one's destination blocks this one so recursively perform all
107 if (other_move.Blocks(destination) && !other_move.IsPending()) {
113 // not be swapped). Since this move's destination is B and there is
122 // pending, so restore its destination.
123 moves_[index].set_destination(destination);
127 if (moves_[index].source()->Equals(destination)) {
137 if (other_move.Blocks(destination)) {
151 // No operand should be the destination for more than one move.
153 LOperand* destination = moves_[i].destination();
155 SLOW_ASSERT(!destination->Equals(moves_[j].destination()));
167 LOperand* destination = moves_[index].destination();
169 // Dispatch on the source and destination operand kinds. Not all
173 if (destination->IsRegister()) {
174 Register dst = cgen_->ToRegister(destination);
177 ASSERT(destination->IsStackSlot());
178 Operand dst = cgen_->ToOperand(destination);
184 if (destination->IsRegister()) {
185 Register dst = cgen_->ToRegister(destination);
188 ASSERT(destination->IsStackSlot());
189 Operand dst = cgen_->ToOperand(destination);
196 if (destination->IsRegister()) {
197 Register dst = cgen_->ToRegister(destination);
204 ASSERT(destination->IsStackSlot());
205 Operand dst = cgen_->ToOperand(destination);
218 if (destination->IsDoubleRegister()) {
219 __ movaps(cgen_->ToDoubleRegister(destination), src);
221 ASSERT(destination->IsDoubleStackSlot());
222 __ movsd(cgen_->ToOperand(destination), src);
226 if (destination->IsDoubleRegister()) {
227 __ movsd(cgen_->ToDoubleRegister(destination), src);
229 ASSERT(destination->IsDoubleStackSlot());
231 __ movsd(cgen_->ToOperand(destination), xmm0);
243 LOperand* destination = moves_[index].destination();
245 // Dispatch on the source and destination operand kinds. Not all
247 if (source->IsRegister() && destination->IsRegister()) {
250 Register dst = cgen_->ToRegister(destination);
253 } else if ((source->IsRegister() && destination->IsStackSlot()) ||
254 (source->IsStackSlot() && destination->IsRegister())) {
257 cgen_->ToRegister(source->IsRegister() ? source : destination);
259 cgen_->ToOperand(source->IsRegister() ? destination : source);
264 } else if ((source->IsStackSlot() && destination->IsStackSlot()) ||
265 (source->IsDoubleStackSlot() && destination->IsDoubleStackSlot())) {
268 Operand dst = cgen_->ToOperand(destination);
274 } else if (source->IsDoubleRegister() && destination->IsDoubleRegister()) {
277 XMMRegister destination_reg = cgen_->ToDoubleRegister(destination);
282 } else if (source->IsDoubleRegister() || destination->IsDoubleRegister()) {
284 ASSERT((source->IsDoubleRegister() && destination->IsDoubleStackSlot()) ||
285 (source->IsDoubleStackSlot() && destination->IsDoubleRegister()));
288 : destination);
289 LOperand* other = source->IsDoubleRegister() ? destination : source;
301 // The swap of source and destination has executed a move from source to
302 // destination.
306 // this move's source or destination needs to have their source
311 moves_[i].set_source(destination);
312 } else if (other_move.Blocks(destination)) {
