Lines Matching refs:rD
2623 Also produce the t/e chars for the 2nd, 3rd, 4th insns, for
7842 void mk_neon_elem_load_to_one_lane( UInt rD, UInt inc, UInt index,
7848 putDRegI64(rD, triop(Iop_SetElem8x8, getDRegI64(rD), mkU8(index),
7852 putDRegI64(rD, triop(Iop_SetElem16x4, getDRegI64(rD), mkU8(index),
7856 putDRegI64(rD, triop(Iop_SetElem32x2, getDRegI64(rD), mkU8(index),
7865 putDRegI64(rD + i * inc,
7867 getDRegI64(rD + i * inc),
7875 putDRegI64(rD + i * inc,
7877 getDRegI64(rD + i * inc),
7885 putDRegI64(rD + i * inc,
7887 getDRegI64(rD + i * inc),
7903 void mk_neon_elem_store_from_one_lane( UInt rD, UInt inc, UInt index,
7910 binop(Iop_GetElem8x8, getDRegI64(rD), mkU8(index)));
7914 binop(Iop_GetElem16x4, getDRegI64(rD), mkU8(index)));
7918 binop(Iop_GetElem32x2, getDRegI64(rD), mkU8(index)));
7927 binop(Iop_GetElem8x8, getDRegI64(rD + i * inc),
7932 binop(Iop_GetElem16x4, getDRegI64(rD + i * inc),
7937 binop(Iop_GetElem32x2, getDRegI64(rD + i * inc),
7955 UInt rD = (INSN(22,22) << 4) | INSN(15,12);
8009 mk_neon_elem_load_to_one_lane(rD, inc, i, N, size, addr);
8011 mk_neon_elem_store_from_one_lane(rD, inc, i, N, size, addr);
8016 DIP("d%u[%u]", rD + j * inc, i);
8059 putDRegI64(rD + r, unop(Iop_Dup8x8,
8064 putDRegI64(rD + r, unop(Iop_Dup16x4,
8069 putDRegI64(rD + r, unop(Iop_Dup32x2,
8079 putDRegI64(rD + r + i * inc,
8087 putDRegI64(rD + r + i * inc,
8095 putDRegI64(rD + r + i * inc,
8112 DIP("d%u[]", rD + r + i * inc);
8193 mk_neon_elem_load_to_one_lane(rD + r, inc, i, N, size, addr);
8195 mk_neon_elem_store_from_one_lane(rD + r, inc, i, N, size, addr);
8225 DIP("d%u-d%u", rD, rD + regs * (N + 1) - 1);
8231 DIP("d%u", rD + r + i * inc);
8437 /* ------------ smulwb<y><c> <Rd>,<Rn>,<Rm> ------------- */
8438 /* ------------ smulwt<y><c> <Rd>,<Rn>,<Rm> ------------- */
8498 /* ------------ pkhbt<c> Rd, Rn, Rm {,LSL #imm} ------------- */
8499 /* ------------ pkhtb<c> Rd, Rn, Rm {,ASR #imm} ------------- */
8559 /* ---------- usat<c> <Rd>,#<imm5>,<Rn>{,<shift>} ----------- */
8617 /* ----------- ssat<c> <Rd>,#<imm5>,<Rn>{,<shift>} ----------- */
8675 /* -------------- usat16<c> <Rd>,#<imm4>,<Rn> --------------- */
8736 /* -------------- uadd16<c> <Rd>,<Rn>,<Rm> -------------- */
8785 /* -------------- sadd16<c> <Rd>,<Rn>,<Rm> -------------- */
8835 /* ---------------- usub16<c> <Rd>,<Rn>,<Rm> ---------------- */
8885 /* -------------- ssub16<c> <Rd>,<Rn>,<Rm> -------------- */
8935 /* ----------------- uadd8<c> <Rd>,<Rn>,<Rm> ---------------- */
8984 /* ------------------- sadd8<c> <Rd>,<Rn>,<Rm> ------------------ */
9034 /* ------------------- usub8<c> <Rd>,<Rn>,<Rm> ------------------ */
9084 /* ------------------- ssub8<c> <Rd>,<Rn>,<Rm> ------------------ */
9134 /* ------------------ qadd8<c> <Rd>,<Rn>,<Rm> ------------------- */
9179 /* ------------------ qsub8<c> <Rd>,<Rn>,<Rm> ------------------- */
9224 /* ------------------ uqadd8<c> <Rd>,<Rn>,<Rm> ------------------ */
9269 /* ------------------ uqsub8<c> <Rd>,<Rn>,<Rm> ------------------ */
9314 /* ----------------- uhadd8<c> <Rd>,<Rn>,<Rm> ------------------- */
9359 /* ----------------- uhadd16<c> <Rd>,<Rn>,<Rm> ------------------- */
9404 /* ----------------- shadd8<c> <Rd>,<Rn>,<Rm> ------------------- */
9449 /* ------------------ qadd16<c> <Rd>,<Rn>,<Rm> ------------------ */
9494 /* ------------------ qsub16<c> <Rd>,<Rn>,<Rm> ------------------ */
9545 /* ------------------- qsax<c> <Rd>,<Rn>,<Rm> ------------------- */
9616 /* ------------------- qasx<c> <Rd>,<Rn>,<Rm> ------------------- */
9684 /* ------------------- sasx<c> <Rd>,<Rn>,<Rm> ------------------- */
9758 /* --------------- smuad, smuadx<c><Rd>,<Rn>,<Rm> --------------- */
9759 /* --------------- smsad, smsadx<c><Rd>,<Rn>,<Rm> --------------- */
9837 /* --------------- smlad{X}<c> <Rd>,<Rn>,<Rm>,<Ra> -------------- */
9838 /* --------------- smlsd{X}<c> <Rd>,<Rn>,<Rm>,<Ra> -------------- */
9928 /* ----- smlabb, smlabt, smlatb, smlatt <Rd>,<Rn>,<Rm>,<Ra> ----- */
9998 /* ----- smlawb, smlawt <Rd>,<Rn>,<Rm>,<Ra> ----- */
10069 /* ------------------- sel<c> <Rd>,<Rn>,<Rm> -------------------- */
10157 /* ----------------- uxtab16<c> Rd,Rn,Rm{,rot} ------------------ */
10220 /* --------------- usad8 Rd,Rn,Rm ---------------- */
10221 /* --------------- usada8 Rd,Rn,Rm,Ra ---------------- */
10223 UInt rD = 99, rN = 99, rM = 99, rA = 99;
10230 rD = INSNT1(11,8);
10232 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM) && rA != 13)
10238 rD = INSNA(19,16);
10242 if (rD != 15 && rN != 15 && rM != 15 /* but rA can be 15 */)
10257 putIRegT( rD, res, condT );
10259 putIRegA( rD, res, condT, Ijk_Boring );
10263 nCC(conq), rD, rN, rM );
10266 nCC(conq), rD, rN, rM, rA );
10273 /* ------------------ qadd<c> <Rd>,<Rn>,<Rm> ------------------- */
10324 /* ------------------ qdadd<c> <Rd>,<Rm>,<Rn> ------------------- */
10383 /* ------------------ qsub<c> <Rd>,<Rn>,<Rm> ------------------- */
10434 /* ------------------ qdsub<c> <Rd>,<Rm>,<Rn> ------------------- */
10493 /* ------------------ uqsub16<c> <Rd>,<Rn>,<Rm> ------------------ */
10538 /* ----------------- shadd16<c> <Rd>,<Rn>,<Rm> ------------------- */
10583 /* ----------------- uhsub8<c> <Rd>,<Rn>,<Rm> ------------------- */
10628 /* ----------------- uhsub16<c> <Rd>,<Rn>,<Rm> ------------------- */
11211 UInt rD = INSN(15,12);
11214 if (rD == 15) {
11216 /* When rD is 15, we are copying the top 4 bits of FPSCR
11228 putIRegT(rD, e, condT);
11230 putIRegA(rD, e, condT, Ijk_Boring);
11231 DIP("fmrx%s r%u, fpscr\n", nCC(conq), rD);
11241 UInt rD = INSN(15,12);
11245 isT ? getIRegT(rD) : getIRegA(rD), condT);
11246 DIP("fmxr%s fpscr, r%u\n", nCC(conq), rD);
11253 // VMOV dM, rD, rN
11256 UInt rD = INSN(15,12); /* lo32 */
11258 if (rD == 15 || rN == 15 || (isT && (rD == 13 || rN == 13))) {
11265 isT ? getIRegT(rD) : getIRegA(rD))),
11267 DIP("vmov%s d%u, r%u, r%u\n", nCC(conq), dM, rD, rN);
11273 // VMOV rD, rN, dM
11276 UInt rD = INSN(15,12); /* lo32 */
11278 if (rD == 15 || rN == 15 || (isT && (rD == 13 || rN == 13))
11279 || rD == rN) {
11288 putIRegT(rD, lo32, condT);
11291 putIRegA(rD, lo32, condT, Ijk_Boring);
11293 DIP("vmov%s r%u, r%u, d%u\n", nCC(conq), rD, rN, dM);
11344 // VMOV rD[x], rT (ARM core register to scalar)
11346 UInt rD = (INSN(7,7) << 4) | INSN(19,16);
11355 putDRegI64(rD, triop(Iop_SetElem8x8,
11356 getDRegI64(rD),
11361 DIP("vmov%s.8 d%u[%u], r%u\n", nCC(conq), rD, index, rT);
11366 putDRegI64(rD, triop(Iop_SetElem16x4,
11367 getDRegI64(rD),
11372 DIP("vmov%s.16 d%u[%u], r%u\n", nCC(conq), rD, index, rT);
11377 putDRegI64(rD, triop(Iop_SetElem32x2,
11378 getDRegI64(rD),
11382 DIP("vmov%s.32 d%u[%u], r%u\n", nCC(conq), rD, index, rT);
11391 // VMOV rT, rD[x]
11448 UInt rD = (INSN(15,12) << 1) | INSN(22,22);
11455 putFReg(rD, unop(Iop_ReinterpI32asF32, mkU32(imm)), condT);
11456 DIP("fconsts%s s%u #%u", nCC(conq), rD, imm8);
11464 UInt rD = INSN(15,12) | (INSN(22,22) << 4);
11471 putDReg(rD, unop(Iop_ReinterpI64asF64, mkU64(imm)), condT);
11472 DIP("fconstd%s d%u #%u", nCC(conq), rD, imm8);
11481 UInt rD = (INSN(7,7) << 4) | INSN(19,16);
11485 if (rT == 15 || (isT && rT == 13) || size == 3 || (Q && (rD & 1))) {
11490 rD >>= 1;
11493 putQReg(rD, unop(Iop_Dup32x4, e), condT);
11496 putQReg(rD, unop(Iop_Dup16x8, unop(Iop_32to16, e)),
11500 putQReg(rD, unop(Iop_Dup8x16, unop(Iop_32to8, e)),
11506 DIP("vdup.%u q%u, r%u\n", 32 / (1<<size), rD, rT);
11510 putDRegI64(rD, unop(Iop_Dup32x2, e), condT);
11513 putDRegI64(rD, unop(Iop_Dup16x4, unop(Iop_32to16, e)),
11517 putDRegI64(rD, unop(Iop_Dup8x8, unop(Iop_32to8, e)),
11523 DIP("vdup.%u d%u, r%u\n", 32 / (1<<size), rD, rT);
11961 UInt rD = INSN(15,12);
11965 if (rD == 15) {
11975 putIRegT(rD, res, condT);
11977 putIRegA(rD, res, condT, Ijk_Boring);
11978 DIP("fmrs%s r%u, s%u\n", nCC(conq), rD, fN);
11981 isT ? getIRegT(rD) : getIRegA(rD)),
11983 DIP("fmsr%s s%u, r%u\n", nCC(conq), fN, rD);
12732 UInt rD = (insn >> 12) & 0xF; /* 15:12 */
12746 case BITS4(0,1,0,0): /* ADD: Rd = Rn + shifter_operand */
12748 case BITS4(0,0,1,0): /* SUB: Rd = Rn - shifter_operand */
12750 case BITS4(0,0,1,1): /* RSB: Rd = shifter_operand - Rn */
12752 case BITS4(0,0,0,0): /* AND: Rd = Rn & shifter_operand */
12754 case BITS4(1,1,0,0): /* OR: Rd = Rn | shifter_operand */
12756 case BITS4(0,0,0,1): /* EOR: Rd = Rn ^ shifter_operand */
12758 case BITS4(1,1,1,0): /* BIC: Rd = Rn & ~shifter_operand */
12803 putIRegA( rD, mkexpr(res), condT, Ijk_Boring );
12834 name, nCC(INSN_COND), bitS ? "s" : "", rD, rN, dis_buf );
12839 case BITS4(1,1,0,1): /* MOV: Rd = shifter_operand */
12840 case BITS4(1,1,1,1): { /* MVN: Rd = not(shifter_operand) */
12867 putIRegA( rD, mkexpr(res), condT, jk );
12875 nCC(INSN_COND), bitS ? "s" : "", rD, dis_buf );
12883 if (rD != 0)
12884 break; /* rD must be zero */
12909 if (rD != 0)
12910 break; /* rD must be zero */
12937 case BITS4(0,1,0,1): /* ADC: Rd = Rn + shifter_operand + oldC */
12939 case BITS4(0,1,1,0): /* SBC: Rd = Rn - shifter_operand - (oldC ^ 1) */
12941 case BITS4(0,1,1,1): /* RSC: Rd = shifter_operand - Rn - (oldC ^ 1) */
12982 putIRegA( rD, mkexpr(res), condT, Ijk_Boring );
13008 name, nCC(INSN_COND), bitS ? "s" : "", rD, rN, dis_buf );
13022 A5-20 1 | 16 cond 0101 UB0L Rn Rd imm12
13023 A5-22 1 | 32 cond 0111 UBOL Rn Rd imm5 sh2 0 Rm
13024 A5-24 2 | 16 cond 0101 UB1L Rn Rd imm12
13025 A5-26 2 | 32 cond 0111 UB1L Rn Rd imm5 sh2 0 Rm
13026 A5-28 3 | 16 cond 0100 UB0L Rn Rd imm12
13027 A5-32 3 | 32 cond 0110 UB0L Rn Rd imm5 sh2 0 Rm
13067 UInt rD = (insn >> 12) & 0xF; /* 15:12 */
13087 if (bL == 1 && rN == rD) goto after_load_store_ubyte_or_word;
13093 if (bL == 1 && rN == rD) goto after_load_store_ubyte_or_word;
13148 assign(rDt, getIRegA(rD));
13181 putIRegA( rD, loadLE(Ity_I32, mkexpr(taT)),
13185 putIRegA( rD, unop(Iop_8Uto32, loadLE(Ity_I8, mkexpr(taT))),
13194 vassert(rD != rN); /* since we just wrote rD */
13203 bB == 0 ? "" : "b", nCC(INSN_COND), rD, dis_buf);
13207 bB == 0 ? "" : "b", nCC(INSN_COND), rD, dis_buf);
13211 bB == 0 ? "" : "b", nCC(INSN_COND), rD, dis_buf);
13223 writeback, and the same register is specified for Rd and Rn,
13243 A5-36 1 | 16 cond 0001 U10L Rn Rd im4h 1SH1 im4l
13244 A5-38 1 | 32 cond 0001 U00L Rn Rd 0000 1SH1 Rm
13245 A5-40 2 | 16 cond 0001 U11L Rn Rd im4h 1SH1 im4l
13246 A5-42 2 | 32 cond 0001 U01L Rn Rd 0000 1SH1 Rm
13247 A5-44 3 | 16 cond 0000 U10L Rn Rd im4h 1SH1 im4l
13248 A5-46 3 | 32 cond 0000 U00L Rn Rd 0000 1SH1 Rm
13289 UInt rD = (insn >> 12) & 0xF; /* 15:12 */
13320 if (bL == 1 && rN == rD) goto after_load_store_sbyte_or_hword;
13326 if (bL == 1 && rN == rD) goto after_load_store_sbyte_or_hword;
13376 storeLE( mkexpr(taT), unop(Iop_32to16, getIRegA(rD)) );
13380 putIRegA( rD, unop(Iop_16Uto32, loadLE(Ity_I16, mkexpr(taT))),
13385 putIRegA( rD, unop(Iop_16Sto32, loadLE(Ity_I16, mkexpr(taT))),
13390 putIRegA( rD, unop(Iop_8Sto32, loadLE(Ity_I8, mkexpr(taT))),
13402 vassert(rD != rN); /* since we just wrote rD */
13408 case 1: DIP("%s%s r%u, %s\n", name, nCC(INSN_COND), rD, dis_buf);
13411 name, nCC(INSN_COND), rD, dis_buf);
13414 name, nCC(INSN_COND), rD, dis_buf);
13426 writeback, and the same register is specified for Rd and Rn,
13631 UInt rD = INSN(15,12);
13642 putIRegA(rD, mkexpr(res), condT, Ijk_Boring);
13643 DIP("clz%s r%u, r%u\n", nCC(INSN_COND), rD, rM);
13653 UInt rD = INSN(19,16);
13656 if (rD == 15 || rM == 15 || rS == 15) {
13674 putIRegA( rD, mkexpr(res), condT, Ijk_Boring );
13683 bitS ? 's' : ' ', nCC(INSN_COND), rD, rM, rS);
13694 UInt rD = INSN(19,16);
13697 if (rD == 15 || rM == 15 || rN == 15) {
13706 putIRegA(rD, mkexpr(res), condT, Ijk_Boring);
13707 DIP("sdiv r%u, r%u, r%u\n", rD, rN, rM);
13716 UInt rD = INSN(19,16);
13719 if (rD == 15 || rM == 15 || rN == 15) {
13728 putIRegA(rD, mkexpr(res), condT, Ijk_Boring);
13729 DIP("udiv r%u, r%u, r%u\n", rD, rN, rM);
13739 UInt rD = INSN(19,16);
13748 if (rD == 15 || rM == 15 || rS == 15 || rN == 15) {
13771 putIRegA( rD, mkexpr(res), condT, Ijk_Boring );
13781 nCC(INSN_COND), rD, rM, rS, rN);
13929 // MRS rD, cpsr
13931 UInt rD = INSN(15,12);
13932 if (rD != 15) {
13934 putIRegA( rD, mkexpr(apsr), condT, Ijk_Boring );
13935 DIP("mrs%s r%u, cpsr\n", nCC(INSN_COND), rD);
13966 UInt rD = INSN(15,12);
13974 if (rD == 15 || rN == 15 || rM == 15 || rN == rM || rN == rD) {
14004 putIRegA(rD, isB ? unop(Iop_8Uto32, mkexpr(tOld)) : mkexpr(tOld),
14007 isB ? "b" : "", nCC(INSN_COND), rD, rM, rN);
14077 UInt rD = INSN(15,12);
14090 if (rD == 15 || rN == 15 || rT == 15
14091 || rD == rN || rD == rT)
14095 if (rD == 15 || (rT & 1) == 1 || rT == 14 || rN == 15
14096 || rD == rN || rD == rT || rD == rT+1)
14119 /* Set rD to 1 on failure, 0 on success. Currently we have
14125 putIRegA(rD, mkexpr(resSC32),
14129 nm, nCC(INSN_COND), rD, rT, rT+1, rN);
14132 nm, nCC(INSN_COND), rD, rT, rN);
14142 UInt rD = INSN(15,12);
14145 if (rD == 15) {
14149 putIRegA(rD,
14151 binop(Iop_And32, getIRegA(rD), mkU32(0xFFFF)),
14154 DIP("movt%s r%u, #0x%04x\n", nCC(INSN_COND), rD, imm16);
14157 putIRegA(rD, mkU32(imm16), condT, Ijk_Boring);
14158 DIP("movw%s r%u, #0x%04x\n", nCC(INSN_COND), rD, imm16);
14176 UInt rD = INSN(15,12);
14227 putIRegA(rD, mkexpr(dstT), condT, Ijk_Boring);
14228 DIP("%s%s r%u, r%u, ROR #%u\n", nm, nCC(INSN_COND), rD, rM, rot);
14237 UInt rD = INSN(15,12);
14241 if (rD == 15 || msb < lsb) {
14253 assign(olddst, getIRegA(rD));
14264 putIRegA(rD, mkexpr(newdst), condT, Ijk_Boring);
14268 nCC(INSN_COND), rD, lsb, msb-lsb+1);
14271 nCC(INSN_COND), rD, rN, lsb, msb-lsb+1);
14281 UInt rD = INSN(15,12);
14287 if (rD == 15 || rN == 15 || msb >= 32) {
14305 putIRegA(rD, mkexpr(res), condT, Ijk_Boring);
14309 nCC(INSN_COND), rD, rN, lsb, wm1 + 1);
14319 A5-36 1 | 16 cond 0001 U100 Rn Rd im4h 11S1 im4l
14320 A5-38 1 | 32 cond 0001 U000 Rn Rd 0000 11S1 Rm
14321 A5-40 2 | 16 cond 0001 U110 Rn Rd im4h 11S1 im4l
14322 A5-42 2 | 32 cond 0001 U010 Rn Rd 0000 11S1 Rm
14323 A5-44 3 | 16 cond 0000 U100 Rn Rd im4h 11S1 im4l
14324 A5-46 3 | 32 cond 0000 U000 Rn Rd 0000 11S1 Rm
14365 UInt rD = (insn >> 12) & 0xF; /* 15:12 */
14371 /* Require rD to be an even numbered register */
14372 if ((rD & 1) != 0)
14390 if (bS == 0 && (rN == rD || rN == rD+1))
14397 if (bS == 0 && (rN == rD || rN == rD+1))
14450 storeLE( binop(Iop_Add32, mkexpr(taT), mkU32(0)), getIRegA(rD+0) );
14451 storeLE( binop(Iop_Add32, mkexpr(taT), mkU32(4)), getIRegA(rD+1) );
14454 putIRegA( rD+0,
14457 putIRegA( rD+1,
14468 vassert(rD+0 != rN); /* since we just wrote rD+0 */
14469 vassert(rD+1 != rN); /* since we just wrote rD+1 */
14476 case 1: DIP("%s%s r%u, %s\n", name, nCC(INSN_COND), rD, dis_buf);
14479 name, nCC(INSN_COND), rD, dis_buf);
14482 name, nCC(INSN_COND), rD, dis_buf);
14497 UInt rD = INSN(15,12);
14501 if (rN == 15/*it's {S,U}XTB*/ || rD == 15 || rM == 15) {
14514 putIRegA(rD, mkexpr(res), condT, Ijk_Boring);
14516 isU ? 'u' : 's', nCC(INSN_COND), rD, rN, rM, rot);
14527 UInt rD = INSN(15,12);
14531 if (rN == 15/*it's {S,U}XTH*/ || rD == 15 || rM == 15) {
14544 putIRegA(rD, mkexpr(res), condT, Ijk_Boring);
14547 isU ? 'u' : 's', nCC(INSN_COND), rD, rN, rM, rot);
14558 UInt rD = INSN(15,12);
14559 if (rM != 15 && rD != 15) {
14563 putIRegA(rD, mkexpr(res), condT, Ijk_Boring);
14565 nCC(INSN_COND), rD, rM);
14572 UInt rD = INSN(15,12);
14574 if (rD != 15 && rM != 15) {
14578 putIRegA(rD, mkexpr(res), condT, Ijk_Boring);
14579 DIP("rbit r%u, r%u\n", rD, rM);
14589 UInt rD = INSN(19,16);
14592 if (rD != 15 && rM != 15 && rN != 15) {
14598 putIRegA(rD, res, condT, Ijk_Boring);
14600 nCC(INSN_COND), bitR ? "r" : "", rD, rN, rM);
14610 UInt rD = INSN(19,16);
14614 if (rD != 15 && rM != 15 && rN != 15) {
14622 putIRegA(rD, res, condT, Ijk_Boring);
14624 nCC(INSN_COND), bitR ? "r" : "", rD, rN, rM, rA);
14647 UInt rD = INSN(15,12);
14648 if (rD <= 14) {
14650 putIRegA(rD, IRExpr_Get(OFFB_TPIDRURO, Ity_I32),
14652 DIP("mrc%s p15,0, r%u, c13, c0, 3\n", nCC(INSN_COND), rD);
15316 /* ---------------- NEGS Rd, Rm ---------------- */
15317 /* Rd = -Rm */
15319 UInt rD = INSN0(2,0);
15324 // rD can never be r15
15325 putIRegT(rD, binop(Iop_Sub32, mkexpr(zero), mkexpr(arg)), condT);
15327 DIP("negs r%u, r%u\n", rD, rM);
15332 /* ---------------- MVNS Rd, Rm ---------------- */
15333 /* Rd = ~Rm */
15335 UInt rD = INSN0(2,0);
15342 // rD can never be r15
15343 putIRegT(rD, mkexpr(res), condT);
15346 DIP("mvns r%u, r%u\n", rD, rM);
15351 /* ---------------- ORRS Rd, Rm ---------------- */
15354 /* ---------------- ANDS Rd, Rm ---------------- */
15357 /* ---------------- EORS Rd, Rm ---------------- */
15360 /* ---------------- MULS Rd, Rm ---------------- */
15363 /* Rd = Rd `op` Rm */
15365 UInt rD = INSN0(2,0);
15371 assign( res, binop(anOp, getIRegT(rD), getIRegT(rM) ));
15373 // rD can never be r15
15374 putIRegT(rD, mkexpr(res), condT);
15377 DIP("%s r%u, r%u\n", anOpNm, rD, rM);
15382 /* ---------------- BICS Rd, Rm ---------------- */
15383 /* Rd = Rd & ~Rm */
15385 UInt rD = INSN0(2,0);
15391 assign( res, binop(Iop_And32, getIRegT(rD),
15394 // rD can never be r15
15395 putIRegT(rD, mkexpr(res), condT);
15398 DIP("bics r%u, r%u\n", rD, rM);
15403 /* ---------------- ADCS Rd, Rm ---------------- */
15404 /* Rd = Rd + Rm + oldC */
15406 UInt rD = INSN0(2,0);
15411 assign(argL, getIRegT(rD));
15417 // rD can never be r15
15418 putIRegT(rD, mkexpr(res), condT);
15421 DIP("adcs r%u, r%u\n", rD, rM);
15426 /* ---------------- SBCS Rd, Rm ---------------- */
15427 /* Rd = Rd - Rm - (oldC ^ 1) */
15429 UInt rD = INSN0(2,0);
15434 assign(argL, getIRegT(rD));
15440 // rD can never be r15
15441 putIRegT(rD, mkexpr(res), condT);
15444 DIP("sbcs r%u, r%u\n", rD, rM);
15449 /* ---------------- UXTB Rd, Rm ---------------- */
15450 /* Rd = 8Uto32(Rm) */
15452 UInt rD = INSN0(2,0);
15453 putIRegT(rD, binop(Iop_And32, getIRegT(rM), mkU32(0xFF)),
15455 DIP("uxtb r%u, r%u\n", rD, rM);
15460 /* ---------------- SXTB Rd, Rm ---------------- */
15461 /* Rd = 8Sto32(Rm) */
15463 UInt rD = INSN0(2,0);
15464 putIRegT(rD, binop(Iop_Sar32,
15468 DIP("sxtb r%u, r%u\n", rD, rM);
15473 /* ---------------- UXTH Rd, Rm ---------------- */
15474 /* Rd = 16Uto32(Rm) */
15476 UInt rD = INSN0(2,0);
15477 putIRegT(rD, binop(Iop_And32, getIRegT(rM), mkU32(0xFFFF)),
15479 DIP("uxth r%u, r%u\n", rD, rM);
15484 /* ---------------- SXTH Rd, Rm ---------------- */
15485 /* Rd = 16Sto32(Rm) */
15487 UInt rD = INSN0(2,0);
15488 putIRegT(rD, binop(Iop_Sar32,
15492 DIP("sxth r%u, r%u\n", rD, rM);
15500 /* ---------------- LSLS Rs, Rd ---------------- */
15501 /* ---------------- LSRS Rs, Rd ---------------- */
15502 /* ---------------- ASRS Rs, Rd ---------------- */
15503 /* ---------------- RORS Rs, Rd ---------------- */
15504 /* Rd = Rd `op` Rs, and set flags */
15506 UInt rD = INSN0(2,0);
15514 assign(rDt, getIRegT(rD));
15520 dis_buf, &res, &resC, rDt, rSt, rD, rS
15526 dis_buf, &res, &resC, rDt, rSt, rD, rS
15532 dis_buf, &res, &resC, rDt, rSt, rD, rS
15538 dis_buf, &res, &resC, rDt, rSt, rD, rS
15546 putIRegT(rD, mkexpr(res), condT);
15549 DIP("%ss r%u, r%u\n", wot, rS, rD);
15555 /* ---------------- REV Rd, Rm ---------------- */
15556 /* ---------------- REV16 Rd, Rm ---------------- */
15558 UInt rD = INSN0(2,0);
15563 putIRegT(rD, mkexpr(res), condT);
15564 DIP("rev%s r%u, r%u\n", isREV ? "" : "16", rD, rM);
15682 /* ---------------- ADD(HI) Rd, Rm ---------------- */
15686 UInt rD = (h1 << 3) | INSN0(2,0);
15688 if (rD == 15 && rM == 15) {
15692 assign( res, binop(Iop_Add32, getIRegT(rD), getIRegT(rM) ));
15693 if (rD != 15) {
15694 putIRegT( rD, mkexpr(res), condT );
15707 DIP("add(hi) r%u, r%u\n", rD, rM);
15714 /* ---------------- CMP(HI) Rd, Rm ---------------- */
15733 /* ---------------- MOV(HI) Rd, Rm ---------------- */
15737 UInt rD = (h1 << 3) | INSN0(2,0);
15738 /* The old ARM ARM seems to disallow the case where both Rd and
15743 if (rD != 15) {
15744 putIRegT( rD, mkexpr(val), condT );
15757 DIP("mov r%u, r%u\n", rD, rM);
15972 /* ---------------- ADDS Rd, Rn, #uimm3 ---------------- */
15973 /* ---------------- SUBS Rd, Rn, #uimm3 ---------------- */
15976 UInt rD = INSN0(2,0);
15982 putIRegT(rD, binop(isSub ? Iop_Sub32 : Iop_Add32,
15987 DIP("%s r%u, r%u, #%u\n", isSub ? "subs" : "adds", rD, rN, uimm3);
15993 /* ---------------- ADDS Rd, Rn, Rm ---------------- */
15994 /* ---------------- SUBS Rd, Rn, Rm ---------------- */
15997 UInt rD = INSN0(2,0);
16003 putIRegT( rD, binop(isSub ? Iop_Sub32 : Iop_Add32,
16008 DIP("%s r%u, r%u, r%u\n", isSub ? "subs" : "adds", rD, rN, rM);
16014 /* ------------- LDR Rd, [Rn, Rm] ------------- */
16015 /* ------------- STR Rd, [Rn, Rm] ------------- */
16016 /* LDR/STR Rd, [Rn + Rm] */
16017 UInt rD = INSN0(2,0);
16029 putIRegT(rD, loadLE(Ity_I32, ea), IRTemp_INVALID);
16031 storeLE(ea, getIRegT(rD));
16035 DIP("%s r%u, [r%u, r%u]\n", isLD ? "ldr" : "str", rD, rN, rM);
16041 /* ------------- LDRH Rd, [Rn, Rm] ------------- */
16042 /* ------------- STRH Rd, [Rn, Rm] ------------- */
16043 /* LDRH/STRH Rd, [Rn + Rm] */
16044 UInt rD = INSN0(2,0);
16056 putIRegT(rD, unop(Iop_16Uto32, loadLE(Ity_I16, ea)),
16059 storeLE( ea, unop(Iop_32to16, getIRegT(rD)) );
16063 DIP("%sh r%u, [r%u, r%u]\n", isLD ? "ldr" : "str", rD, rN, rM);
16068 /* ------------- LDRSH Rd, [Rn, Rm] ------------- */
16069 /* LDRSH Rd, [Rn + Rm] */
16070 UInt rD = INSN0(2,0);
16080 putIRegT(rD, unop(Iop_16Sto32, loadLE(Ity_I16, ea)),
16084 DIP("ldrsh r%u, [r%u, r%u]\n", rD, rN, rM);
16089 /* ------------- LDRSB Rd, [Rn, Rm] ------------- */
16090 /* LDRSB Rd, [Rn + Rm] */
16091 UInt rD = INSN0(2,0);
16101 putIRegT(rD, unop(Iop_8Sto32, loadLE(Ity_I8, ea)),
16105 DIP("ldrsb r%u, [r%u, r%u]\n", rD, rN, rM);
16111 /* ------------- LDRB Rd, [Rn, Rm] ------------- */
16112 /* ------------- STRB Rd, [Rn, Rm] ------------- */
16113 /* LDRB/STRB Rd, [Rn + Rm] */
16114 UInt rD = INSN0(2,0);
16126 putIRegT(rD, unop(Iop_8Uto32, loadLE(Ity_I8, ea)),
16129 storeLE( ea, unop(Iop_32to8, getIRegT(rD)) );
16133 DIP("%sb r%u, [r%u, r%u]\n", isLD ? "ldr" : "str", rD, rN, rM);
16167 /* ---------------- ADD rD, PC, #imm8 * 4 ---------------- */
16169 /* rD = align4(PC) + imm8 * 4 */
16170 UInt rD = INSN0(10,8);
16172 putIRegT(rD, binop(Iop_Add32,
16176 DIP("add r%u, pc, #%u\n", rD, imm8 * 4);
16181 /* ---------------- ADD rD, SP, #imm8 * 4 ---------------- */
16182 UInt rD = INSN0(10,8);
16184 putIRegT(rD, binop(Iop_Add32, getIRegT(13), mkU32(imm8 * 4)),
16186 DIP("add r%u, r13, #%u\n", rD, imm8 * 4);
16206 UInt rD = INSN0(10,8);
16214 putIRegT(rD, mkexpr(res), condT);
16217 DIP("movs r%u, #%u\n", rD, uimm8);
16222 /* ------------- LDR Rd, [PC, #imm8 * 4] ------------- */
16223 /* LDR Rd, [align4(PC) + imm8 * 4] */
16224 UInt rD = INSN0(10,8);
16236 putIRegT(rD, loadLE(Ity_I32, mkexpr(ea)),
16240 DIP("ldr r%u, [pc, #%u]\n", rD, imm8 * 4);
16246 /* ------------- LDR Rd, [Rn, #imm5 * 4] ------------- */
16247 /* ------------- STR Rd, [Rn, #imm5 * 4] ------------- */
16248 /* LDR/STR Rd, [Rn + imm5 * 4] */
16249 UInt rD = INSN0(2,0);
16261 putIRegT(rD, loadLE(Ity_I32, ea), IRTemp_INVALID);
16263 storeLE( ea, getIRegT(rD) );
16267 DIP("%s r%u, [r%u, #%u]\n", isLD ? "ldr" : "str", rD, rN, imm5 * 4);
16273 /* ------------- LDRH Rd, [Rn, #imm5 * 2] ------------- */
16274 /* ------------- STRH Rd, [Rn, #imm5 * 2] ------------- */
16275 /* LDRH/STRH Rd, [Rn + imm5 * 2] */
16276 UInt rD = INSN0(2,0);
16288 putIRegT(rD, unop(Iop_16Uto32, loadLE(Ity_I16, ea)),
16291 storeLE( ea, unop(Iop_32to16, getIRegT(rD)) );
16295 DIP("%sh r%u, [r%u, #%u]\n", isLD ? "ldr" : "str", rD, rN, imm5 * 2);
16301 /* ------------- LDRB Rd, [Rn, #imm5] ------------- */
16302 /* ------------- STRB Rd, [Rn, #imm5] ------------- */
16303 /* LDRB/STRB Rd, [Rn + imm5] */
16304 UInt rD = INSN0(2,0);
16316 putIRegT(rD, unop(Iop_8Uto32, loadLE(Ity_I8, ea)),
16319 storeLE( ea, unop(Iop_32to8, getIRegT(rD)) );
16323 DIP("%sb r%u, [r%u, #%u]\n", isLD ? "ldr" : "str", rD, rN, imm5);
16329 /* ------------- LDR Rd, [SP, #imm8 * 4] ------------- */
16330 /* ------------- STR Rd, [SP, #imm8 * 4] ------------- */
16331 /* LDR/STR Rd, [SP + imm8 * 4] */
16332 UInt rD = INSN0(10,8);
16343 putIRegT(rD, loadLE(Ity_I32, ea), IRTemp_INVALID);
16345 rD));
16349 DIP("%s r%u, [sp, #%u]\n", isLD ? "ldr" : "str", rD, imm8 * 4);
16448 /* ---------------- LSLS Rd, Rm, #imm5 ---------------- */
16449 /* ---------------- LSRS Rd, Rm, #imm5 ---------------- */
16450 /* ---------------- ASRS Rd, Rm, #imm5 ---------------- */
16451 UInt rD = INSN0(2,0);
16486 putIRegT(rD, mkexpr(res), condT);
16490 DIP("%ss r%u, r%u, #%u\n", wot, rD, rM, imm5);
16706 /* -------------- (T3) ADD{S}.W Rd, Rn, #constT -------------- */
16712 UInt rD = INSN1(11,8);
16713 Bool valid = !isBadRegT(rN) && !isBadRegT(rD);
16715 if (!valid && rD <= 14 && rN == 13)
16725 putIRegT(rD, mkexpr(res), condT);
16729 bS == 1 ? "s" : "", rD, rN, imm32);
16734 /* ---------------- (T4) ADDW Rd, Rn, #uimm12 -------------- */
16739 UInt rD = INSN1(11,8);
16740 Bool valid = !isBadRegT(rN) && !isBadRegT(rD);
16742 if (!valid && rD <= 14 && rN == 13)
16752 putIRegT(rD, mkexpr(res), condT);
16753 DIP("addw r%u, r%u, #%u\n", rD, rN, imm12);
16811 /* -------------- (T3) SUB{S}.W Rd, Rn, #constT -------------- */
16812 /* -------------- (T3) RSB{S}.W Rd, Rn, #constT -------------- */
16820 UInt rD = INSN1(11,8);
16821 Bool valid = !isBadRegT(rN) && !isBadRegT(rD);
16824 if (!valid && !isRSB && rN == 13 && rD != 15)
16836 putIRegT(rD, mkexpr(res), condT);
16844 isRSB ? "rsb" : "sub", bS == 1 ? "s" : "", rD, rN, imm32);
16849 /* -------------- (T4) SUBW Rd, Rn, #uimm12 ------------------- */
16854 UInt rD = INSN1(11,8);
16855 Bool valid = !isBadRegT(rN) && !isBadRegT(rD);
16857 if (!valid && rD == 13 && rN == 13)
16867 putIRegT(rD, mkexpr(res), condT);
16868 DIP("subw r%u, r%u, #%u\n", rD, rN, imm12);
16873 /* -------------- (T1) ADC{S}.W Rd, Rn, #constT -------------- */
16874 /* -------------- (T1) SBC{S}.W Rd, Rn, #constT -------------- */
16879 /* ADC: Rd = Rn + constT + oldC */
16880 /* SBC: Rd = Rn - constT - (oldC ^ 1) */
16883 UInt rD = INSN1(11,8);
16884 if (!isBadRegT(rN) && !isBadRegT(rD)) {
16901 putIRegT(rD, mkexpr(res), condT);
16912 putIRegT(rD, mkexpr(res), condT);
16921 nm, bS == 1 ? "s" : "", rD, rN, imm32);
16926 /* -------------- (T1) ORR{S}.W Rd, Rn, #constT -------------- */
16927 /* -------------- (T1) AND{S}.W Rd, Rn, #constT -------------- */
16928 /* -------------- (T1) BIC{S}.W Rd, Rn, #constT -------------- */
16929 /* -------------- (T1) EOR{S}.W Rd, Rn, #constT -------------- */
16939 UInt rD = INSN1(11,8);
16940 if (!isBadRegT(rN) && !isBadRegT(rD)) {
16962 putIRegT(rD, mkexpr(res), condT);
16974 nm, bS == 1 ? "s" : "", rD, rN, imm32);
16979 /* ---------- (T3) ADD{S}.W Rd, Rn, Rm, {shift} ---------- */
16980 /* ---------- (T3) SUB{S}.W Rd, Rn, Rm, {shift} ---------- */
16981 /* ---------- (T3) RSB{S}.W Rd, Rn, Rm, {shift} ---------- */
16988 UInt rD = INSN1(11,8);
16994 Bool valid = !isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM);
16998 && rD != 15 && rN == 13 && imm5 <= 3 && how == 0) {
17004 && rD != 15 && rN == 13 && imm5 == 0 && how == 0) {
17035 putIRegT(rD, mkexpr(res), condT);
17053 nm, bS ? "s" : "", rD, rN, dis_buf);
17058 /* ---------- (T3) ADC{S}.W Rd, Rn, Rm, {shift} ---------- */
17059 /* ---------- (T2) SBC{S}.W Rd, Rn, Rm, {shift} ---------- */
17064 /* ADC: Rd = Rn + shifter_operand + oldC */
17065 /* SBC: Rd = Rn - shifter_operand - (oldC ^ 1) */
17067 UInt rD = INSN1(11,8);
17069 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
17097 putIRegT(rD, mkexpr(res), condT);
17108 putIRegT(rD, mkexpr(res), condT);
17118 nm, bS ? "s" : "", rD, rN, dis_buf);
17123 /* ---------- (T3) AND{S}.W Rd, Rn, Rm, {shift} ---------- */
17124 /* ---------- (T3) ORR{S}.W Rd, Rn, Rm, {shift} ---------- */
17125 /* ---------- (T3) EOR{S}.W Rd, Rn, Rm, {shift} ---------- */
17126 /* ---------- (T3) BIC{S}.W Rd, Rn, Rm, {shift} ---------- */
17127 /* ---------- (T1) ORN{S}.W Rd, Rn, Rm, {shift} ---------- */
17136 UInt rD = INSN1(11,8);
17138 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
17178 putIRegT(rD, mkexpr(res), condT);
17187 nm, bS ? "s" : "", rD, rN, dis_buf);
17192 /* -------------- (T?) LSL{S}.W Rd, Rn, Rm -------------- */
17193 /* -------------- (T?) LSR{S}.W Rd, Rn, Rm -------------- */
17194 /* -------------- (T?) ASR{S}.W Rd, Rn, Rm -------------- */
17195 /* -------------- (T?) ROR{S}.W Rd, Rn, Rm -------------- */
17201 UInt rD = INSN1(11,8);
17204 Bool valid = !isBadRegT(rN) && !isBadRegT(rM) && !isBadRegT(rD);
17221 putIRegT(rD, mkexpr(res), condT);
17227 nm, bS ? "s" : "", rD, rN, rM);
17232 /* ------------ (T?) MOV{S}.W Rd, Rn, {shift} ------------ */
17233 /* ------------ (T?) MVN{S}.W Rd, Rn, {shift} ------------ */
17236 UInt rD = INSN1(11,8);
17238 if (!isBadRegT(rD) && !isBadRegT(rN)) {
17257 putIRegT(rD, mkexpr(res), condT);
17264 isMVN ? "mvn" : "mov", bS ? "s" : "", rD, dis_buf);
17343 /* -------------- (T2) MOV{S}.W Rd, #constT -------------- */
17344 /* -------------- (T2) MVN{S}.W Rd, #constT -------------- */
17350 UInt rD = INSN1(11,8);
17351 if (!isBadRegT(rD)) {
17358 putIRegT(rD, mkexpr(res), condT);
17370 isMVN ? "mvn" : "mov", bS ? "s" : "", rD, imm32);
17375 /* -------------- (T3) MOVW Rd, #imm16 -------------- */
17379 UInt rD = INSN1(11,8);
17380 if (!isBadRegT(rD)) {
17383 putIRegT(rD, mkU32(imm16), condT);
17384 DIP("movw r%u, #%u\n", rD, imm16);
17389 /* ---------------- MOVT Rd, #imm16 ---------------- */
17393 UInt rD = INSN1(11,8);
17394 if (!isBadRegT(rD)) {
17400 binop(Iop_And32, getIRegT(rD), mkU32(0xFFFF)),
17402 putIRegT(rD, mkexpr(res), condT);
17403 DIP("movt r%u, #%u\n", rD, imm16);
18081 UInt rD = INSN1(11,8);
18085 if (!isBadRegT(rD) && !isBadRegT(rN) && msb <= 31) {
18102 putIRegT(rD, mkexpr(res), condT);
18105 isU ? "ubfx" : "sbfx", rD, rN, lsb, wm1 + 1);
18126 UInt rD = INSN1(11,8);
18129 if (!isBadRegT(rD) && !isBadRegT(rM)) {
18185 putIRegT(rD, mkexpr(dstT), condT);
18186 DIP("%s r%u, r%u, ror #%u\n", nm, rD, rM, 8 * rot);
18191 /* -------------- MUL.W Rd, Rn, Rm -------------- */
18195 UInt rD = INSN1(11,8);
18197 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
18200 putIRegT(rD, mkexpr(res), condT);
18201 DIP("mul.w r%u, r%u, r%u\n", rD, rN, rM);
18206 /* -------------- SDIV.W Rd, Rn, Rm -------------- */
18210 UInt rD = INSN1(11,8);
18212 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
18219 putIRegT(rD, mkexpr(res), condT);
18220 DIP("sdiv.w r%u, r%u, r%u\n", rD, rN, rM);
18225 /* -------------- UDIV.W Rd, Rn, Rm -------------- */
18229 UInt rD = INSN1(11,8);
18231 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
18238 putIRegT(rD, mkexpr(res), condT);
18239 DIP("udiv.w r%u, r%u, r%u\n", rD, rN, rM);
18271 UInt rD = INSN1(11,8);
18273 if (!isBadRegT(rD) && !isBadRegT(rN)
18281 putIRegT(rD, mkexpr(res), condT);
18283 isMLA ? "mla" : "mls", rD, rN, rM, rA);
18291 /* rD = align4(PC) + imm32 */
18292 UInt rD = INSN1(11,8);
18293 if (!isBadRegT(rD)) {
18296 putIRegT(rD, binop(Iop_Add32,
18300 DIP("add r%u, pc, #%u\n", rD, imm32);
18343 /* rD = align4(PC) - imm32 */
18344 UInt rD = INSN1(11,8);
18345 if (!isBadRegT(rD)) {
18348 putIRegT(rD, binop(Iop_Sub32,
18352 DIP("sub r%u, pc, #%u\n", rD, imm32);
18360 UInt rD = INSN1(11,8);
18364 if (isBadRegT(rD) || rN == 13 || msb < lsb) {
18376 assign(olddst, getIRegT(rD));
18387 putIRegT(rD, mkexpr(newdst), condT);
18391 rD, lsb, msb-lsb+1);
18394 rD, rN, lsb, msb-lsb+1);
18408 UInt rD = INSN1(11,8);
18411 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
18422 putIRegT(rD, mkexpr(res), condT);
18424 isU ? 'u' : 's', rD, rN, rM, rot);
18437 UInt rD = INSN1(11,8);
18440 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
18451 putIRegT(rD, mkexpr(res), condT);
18453 isU ? 'u' : 's', rD, rN, rM, rot);
18463 UInt rD = INSN1(11,8);
18465 if (!isBadRegT(rD) && !isBadRegT(rM1) && rM1 == rM2) {
18476 putIRegT(rD, mkexpr(res), condT);
18477 DIP("clz r%u, r%u\n", rD, rM1);
18487 UInt rD = INSN1(11,8);
18489 if (!isBadRegT(rD) && !isBadRegT(rM1) && rM1 == rM2) {
18493 putIRegT(rD, mkexpr(res), condT);
18494 DIP("rbit r%u, r%u\n", rD, rM1);
18506 UInt rD = INSN1(11,8);
18509 if (!isBadRegT(rD) && !isBadRegT(rM1) && rM1 == rM2) {
18513 putIRegT(rD, mkexpr(res), condT);
18514 DIP("rev%s r%u, r%u\n", isREV ? "" : "16", rD, rM1);
18538 UInt rD = INSN1(11,8);
18539 if (!isBadRegT(rD)) {
18541 putIRegT( rD, mkexpr(apsr), condT );
18542 DIP("mrs r%u, cpsr\n", rD);
18615 UInt rD = INSN1(11,8);
18617 if (!isBadRegT(rD) && !isBadRegT(rT) && rN != 15
18618 && rD != rN && rD != rT) {
18629 /* Set rD to 1 on failure, 0 on success. Currently we have
18634 putIRegT(rD, mkexpr(resSC32), IRTemp_INVALID);
18635 DIP("strex r%u, r%u, [r%u, #+%u]\n", rD, rT, rN, imm8 * 4);
18645 UInt rD = INSN1(3,0);
18647 if (!isBadRegT(rD) && !isBadRegT(rT) && rN != 15
18648 && rD != rN && rD != rT) {
18658 /* Set rD to 1 on failure, 0 on success. Currently we have
18663 putIRegT(rD, mkexpr(resSC32), IRTemp_INVALID);
18664 DIP("strex%c r%u, r%u, [r%u]\n", isH ? 'h' : 'b', rD, rT, rN);
18674 UInt rD = INSN1(3,0);
18675 if (!isBadRegT(rD) && !isBadRegT(rT) && !isBadRegT(rT2)
18676 && rN != 15 && rD != rN && rD != rT && rD != rT) {
18688 /* Set rD to 1 on failure, 0 on success. Currently we have
18693 putIRegT(rD, mkexpr(resSC32), IRTemp_INVALID);
18694 DIP("strexd r%u, r%u, r%u, [r%u]\n", rD, rT, rT2, rN);
18781 UInt rD = INSN1(15,12);
18782 if (!isBadRegT(rD)) {
18783 putIRegT(rD, IRExpr_Get(OFFB_TPIDRURO, Ity_I32), IRTemp_INVALID);
18784 DIP("mrc p15,0, r%u, c13, c0, 3\n", rD);
18813 UInt rD = INSN1(11,8);
18816 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
18822 putIRegT(rD, res, condT);
18824 bitR ? "r" : "", rD, rN, rM);
18835 UInt rD = INSN1(11,8);
18838 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM) && (rA != 13)) {
18846 putIRegT(rD, res, condT);
18848 bitR ? "r" : "", rD, rN, rM, rA);
