Lines Matching refs:rM
1734 UInt rM /* only for debug printing */
1742 DIS(buf, "r%u", rM);
1754 DIS(buf, "r%u, LSL #%u", rM, shift_amt);
1764 UInt rM, UInt rS /* only for debug printing */
1769 // res = amt < 32 ? Rm << amt : 0
1771 // amt in 1..32 ? Rm[32-amt] : 0
1778 Rm[(32-amt) & 31]),
1813 // (Rm << (Rs & 31)) & (((Rs & 255) - 32) >>s 31)
1830 DIS(buf, "r%u, LSL r%u", rM, rS);
1839 UInt rM /* only for debug printing */
1845 // newC = Rm[31]
1853 DIS(buf, "r%u, LSR #0(a.k.a. 32)", rM);
1856 // res = Rm >>u shift_amt
1857 // newC = Rm[shift_amt - 1]
1868 DIS(buf, "r%u, LSR #%u", rM, shift_amt);
1878 UInt rM, UInt rS /* only for debug printing */
1883 // res = amt < 32 ? Rm >>u amt : 0
1885 // amt in 1..32 ? Rm[amt-1] : 0
1892 Rm[(amt-1) & 31]),
1925 // (Rm >>u (Rs & 31)) & (((Rs & 255) - 32) >>s 31)
1942 DIS(buf, "r%u, LSR r%u", rM, rS);
1951 UInt rM /* only for debug printing */
1956 // res = Rm >>s 31
1957 // newC = Rm[31]
1965 DIS(buf, "r%u, ASR #0(a.k.a. 32)", rM);
1968 // res = Rm >>s shift_amt
1969 // newC = Rm[shift_amt - 1]
1980 DIS(buf, "r%u, ASR #%u", rM, shift_amt);
1990 UInt rM, UInt rS /* only for debug printing */
1995 // res = amt < 32 ? Rm >>s amt : Rm >>s 31
1997 // amt in 1..32 ? Rm[amt-1] : Rm[31]
2003 Rm[31],
2004 Rm[(amt-1) & 31])
2043 // (Rm >>s (amt <u 32 ? amt : 31))
2057 DIS(buf, "r%u, ASR r%u", rM, rS);
2066 UInt rM, UInt rS /* only for debug printing */
2071 // shop = Rm `ror` (amt & 31)
2072 // shco = amt == 0 ? oldC : Rm[(amt-1) & 31]
2121 DIS(buf, "r%u, ROR r#%u", rM, rS);
2147 UInt rM /* only for debug printing */
2157 buf, res, newC, rMt, shift_amt, rM
2163 buf, res, newC, rMt, shift_amt, rM
2169 buf, res, newC, rMt, shift_amt, rM
2178 // res = (oldC << 31) | (Rm >>u 1)
2179 // newC = Rm[0]
2189 DIS(buf, "r%u, RRX", rM);
2192 // res = Rm `ror` shift_amt
2193 // newC = Rm[shift_amt - 1]
2207 DIS(buf, "r%u, ROR #%u", rM, shift_amt);
2240 UInt rM, /* only for debug printing */
2248 buf, res, newC, rMt, rSt, rM, rS
2254 buf, res, newC, rMt, rSt, rM, rS
2260 buf, res, newC, rMt, rSt, rM, rS
2266 buf, res, newC, rMt, rSt, rM, rS
2331 /* Rm (3:0) shifted (6:5) by immediate (11:7) */
2333 UInt rM = (insn_11_0 >> 0) & 0xF;
2337 assign(rMt, getIRegA(rM));
2342 buf, shop, shco, rMt, how, shift_amt, rM
2349 /* Rm (3:0) shifted (6:5) by Rs (11:8) */
2350 UInt rM = (insn_11_0 >> 0) & 0xF;
2360 assign(rMt, getIRegA(rM));
2364 buf, shop, shco, rMt, how, rSt, rM, rS
2395 IRExpr* mk_EA_reg_plusminus_shifted_reg ( UInt rN, UInt bU, UInt rM,
2401 vassert(rM < 16);
2409 index = binop(Iop_Shl32, getIRegA(rM), mkU8(imm5));
2410 DIS(buf, "[r%u, %c r%u LSL #%u]", rN, opChar, rM, imm5);
2417 index = binop(Iop_Shr32, getIRegA(rM), mkU8(imm5));
2420 rN, opChar, rM, imm5 == 0 ? 32 : imm5);
2426 index = binop(Iop_Sar32, getIRegA(rM), mkU8(31));
2429 index = binop(Iop_Sar32, getIRegA(rM), mkU8(imm5));
2432 rN, opChar, rM, imm5 == 0 ? 32 : imm5);
2438 assign(rmT, getIRegA(rM));
2443 DIS(buf, "[r%u, %cr%u, RRX]", rN, opChar, rM);
2446 assign(rmT, getIRegA(rM));
2451 DIS(buf, "[r%u, %cr%u, ROR #%u]", rN, opChar, rM, imm5);
2482 IRExpr* mk_EA_reg_plusminus_reg ( UInt rN, UInt bU, UInt rM,
2487 vassert(rM < 16);
2489 IRExpr* index = getIRegA(rM);
2490 DIS(buf, "[r%u, %c r%u]", rN, opChar, rM);
7957 UInt rM = INSN(3,0);
7977 assign(initialRm, isT ? getIRegT(rM) : getIRegA(rM));
8019 if (rM != 13 && rM != 15) {
8020 DIP(", r%u\n", rM);
8022 DIP("%s\n", (rM != 15) ? "!" : "");
8116 if (rM != 13 && rM != 15) {
8117 DIP(", r%u\n", rM);
8119 DIP("%s\n", (rM != 15) ? "!" : "");
8123 if (rM != 15) {
8124 if (rM == 13) {
8203 if (rM != 15) {
8204 if (rM == 13) {
8236 if (rM != 13 && rM != 15) {
8237 DIP(", r%u\n", rM);
8239 DIP("%s\n", (rM != 15) ? "!" : "");
8437 /* ------------ smulwb<y><c> <Rd>,<Rn>,<Rm> ------------- */
8438 /* ------------ smulwt<y><c> <Rd>,<Rn>,<Rm> ------------- */
8498 /* ------------ pkhbt<c> Rd, Rn, Rm {,LSL #imm} ------------- */
8499 /* ------------ pkhtb<c> Rd, Rn, Rm {,ASR #imm} ------------- */
8736 /* -------------- uadd16<c> <Rd>,<Rn>,<Rm> -------------- */
8785 /* -------------- sadd16<c> <Rd>,<Rn>,<Rm> -------------- */
8835 /* ---------------- usub16<c> <Rd>,<Rn>,<Rm> ---------------- */
8885 /* -------------- ssub16<c> <Rd>,<Rn>,<Rm> -------------- */
8935 /* ----------------- uadd8<c> <Rd>,<Rn>,<Rm> ---------------- */
8984 /* ------------------- sadd8<c> <Rd>,<Rn>,<Rm> ------------------ */
9034 /* ------------------- usub8<c> <Rd>,<Rn>,<Rm> ------------------ */
9084 /* ------------------- ssub8<c> <Rd>,<Rn>,<Rm> ------------------ */
9134 /* ------------------ qadd8<c> <Rd>,<Rn>,<Rm> ------------------- */
9179 /* ------------------ qsub8<c> <Rd>,<Rn>,<Rm> ------------------- */
9224 /* ------------------ uqadd8<c> <Rd>,<Rn>,<Rm> ------------------ */
9269 /* ------------------ uqsub8<c> <Rd>,<Rn>,<Rm> ------------------ */
9314 /* ----------------- uhadd8<c> <Rd>,<Rn>,<Rm> ------------------- */
9359 /* ----------------- uhadd16<c> <Rd>,<Rn>,<Rm> ------------------- */
9404 /* ----------------- shadd8<c> <Rd>,<Rn>,<Rm> ------------------- */
9449 /* ------------------ qadd16<c> <Rd>,<Rn>,<Rm> ------------------ */
9494 /* ------------------ qsub16<c> <Rd>,<Rn>,<Rm> ------------------ */
9545 /* ------------------- qsax<c> <Rd>,<Rn>,<Rm> ------------------- */
9616 /* ------------------- qasx<c> <Rd>,<Rn>,<Rm> ------------------- */
9684 /* ------------------- sasx<c> <Rd>,<Rn>,<Rm> ------------------- */
9758 /* --------------- smuad, smuadx<c><Rd>,<Rn>,<Rm> --------------- */
9759 /* --------------- smsad, smsadx<c><Rd>,<Rn>,<Rm> --------------- */
9837 /* --------------- smlad{X}<c> <Rd>,<Rn>,<Rm>,<Ra> -------------- */
9838 /* --------------- smlsd{X}<c> <Rd>,<Rn>,<Rm>,<Ra> -------------- */
9928 /* ----- smlabb, smlabt, smlatb, smlatt <Rd>,<Rn>,<Rm>,<Ra> ----- */
9998 /* ----- smlawb, smlawt <Rd>,<Rn>,<Rm>,<Ra> ----- */
10069 /* ------------------- sel<c> <Rd>,<Rn>,<Rm> -------------------- */
10157 /* ----------------- uxtab16<c> Rd,Rn,Rm{,rot} ------------------ */
10220 /* --------------- usad8 Rd,Rn,Rm ---------------- */
10221 /* --------------- usada8 Rd,Rn,Rm,Ra ---------------- */
10223 UInt rD = 99, rN = 99, rM = 99, rA = 99;
10231 rM = INSNT1(3,0);
10232 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM) && rA != 13)
10240 rM = INSNA(11,8);
10242 if (rD != 15 && rN != 15 && rM != 15 /* but rA can be 15 */)
10250 IRExpr* rMe = isT ? getIRegT(rM) : getIRegA(rM);
10263 nCC(conq), rD, rN, rM );
10266 nCC(conq), rD, rN, rM, rA );
10273 /* ------------------ qadd<c> <Rd>,<Rn>,<Rm> ------------------- */
10324 /* ------------------ qdadd<c> <Rd>,<Rm>,<Rn> ------------------- */
10383 /* ------------------ qsub<c> <Rd>,<Rn>,<Rm> ------------------- */
10434 /* ------------------ qdsub<c> <Rd>,<Rm>,<Rn> ------------------- */
10493 /* ------------------ uqsub16<c> <Rd>,<Rn>,<Rm> ------------------ */
10538 /* ----------------- shadd16<c> <Rd>,<Rn>,<Rm> ------------------- */
10583 /* ----------------- uhsub8<c> <Rd>,<Rn>,<Rm> ------------------- */
10628 /* ----------------- uhsub16<c> <Rd>,<Rn>,<Rm> ------------------- */
11299 // VMOV sD, sD+1, rN, rM
11303 UInt rM = INSN(19,16);
11304 if (rM == 15 || rN == 15 || (isT && (rM == 13 || rN == 13))
11312 unop(Iop_ReinterpI32asF32, isT ? getIRegT(rM) : getIRegA(rM)),
11315 nCC(conq), sD, sD + 1, rN, rM);
11320 // VMOV rN, rM, sD, sD+1
11324 UInt rM = INSN(19,16);
11325 if (rM == 15 || rN == 15 || (isT && (rM == 13 || rN == 13))
11326 || sD == 31 || rN == rM) {
11333 putIRegT(rM, res1, condT);
11336 putIRegA(rM, res1, condT, Ijk_Boring);
11339 nCC(conq), rN, rM, sD, sD + 1);
11574 IRExpr* rm = get_FAKE_roundingmode(); /* XXXROUNDINGFIXME */
11577 putDReg(dD, triop(Iop_AddF64, rm,
11579 triop(Iop_MulF64, rm, getDReg(dN),
11585 putDReg(dD, triop(Iop_AddF64, rm,
11588 triop(Iop_MulF64, rm, getDReg(dN),
11594 putDReg(dD, triop(Iop_AddF64, rm,
11596 triop(Iop_MulF64, rm, getDReg(dN),
11602 putDReg(dD, triop(Iop_AddF64, rm,
11605 triop(Iop_MulF64, rm, getDReg(dN),
11611 putDReg(dD, triop(Iop_MulF64, rm, getDReg(dN), getDReg(dM)),
11617 rm, getDReg(dN),
11623 putDReg(dD, triop(Iop_AddF64, rm, getDReg(dN), getDReg(dM)),
11628 putDReg(dD, triop(Iop_SubF64, rm, getDReg(dN), getDReg(dM)),
11633 putDReg(dD, triop(Iop_DivF64, rm, getDReg(dN), getDReg(dM)),
11743 IRExpr* rm = get_FAKE_roundingmode(); /* XXXROUNDINGFIXME */
11744 putDReg(dD, binop(Iop_SqrtF64, rm, getDReg(dM)), condT);
12039 IRExpr* rm = get_FAKE_roundingmode(); /* XXXROUNDINGFIXME */
12042 rm,
12044 triop(Iop_MulF32, rm, getFReg(fN), getFReg(fM))),
12049 putFReg(fD, triop(Iop_AddF32, rm,
12052 triop(Iop_MulF32, rm, getFReg(fN),
12058 putFReg(fD, triop(Iop_AddF32, rm,
12060 triop(Iop_MulF32, rm, getFReg(fN), getFReg(fM))),
12065 putFReg(fD, triop(Iop_AddF32, rm,
12068 triop(Iop_MulF32, rm,
12075 putFReg(fD, triop(Iop_MulF32, rm, getFReg(fN), getFReg(fM)),
12081 triop(Iop_MulF32, rm, getFReg(fN),
12087 putFReg(fD, triop(Iop_AddF32, rm, getFReg(fN), getFReg(fM)),
12092 putFReg(fD, triop(Iop_SubF32, rm, getFReg(fN), getFReg(fM)),
12097 putFReg(fD, triop(Iop_DivF32, rm, getFReg(fN), getFReg(fM)),
12214 IRExpr* rm = get_FAKE_roundingmode(); /* XXXROUNDINGFIXME */
12215 putFReg(fD, binop(Iop_SqrtF32, rm, getFReg(fM)), condT);
12388 IRExpr* rm = mkU32(Irrm_NEAREST);
12390 rm, as_F64,
12391 triop(Iop_AddF64, rm, mkexpr(scale), mkexpr(scale)));
12459 UInt rM = INSN(3,0);
12463 if (rM != 15) {
12464 IRExpr* eaE = mk_EA_reg_plusminus_shifted_reg(rN, bU, rM,
13023 A5-22 1 | 32 cond 0111 UBOL Rn Rd imm5 sh2 0 Rm
13025 A5-26 2 | 32 cond 0111 UB1L Rn Rd imm5 sh2 0 Rm
13027 A5-32 3 | 32 cond 0110 UB0L Rn Rd imm5 sh2 0 Rm
13035 32 Rn +/- Rm sh2 imm5
13068 UInt rM = (insn >> 0) & 0xF; /* 3:0 */
13083 if (rM == 15) goto after_load_store_ubyte_or_word;
13090 if (rM == 15) goto after_load_store_ubyte_or_word;
13092 if (rN == rM) goto after_load_store_ubyte_or_word;
13116 eaE = mk_EA_reg_plusminus_shifted_reg( rN, bU, rM, sh2, imm5,
13244 A5-38 1 | 32 cond 0001 U00L Rn Rd 0000 1SH1 Rm
13246 A5-42 2 | 32 cond 0001 U01L Rn Rd 0000 1SH1 Rm
13248 A5-46 3 | 32 cond 0000 U00L Rn Rd 0000 1SH1 Rm
13256 32 Rn +/- Rm
13290 UInt rM = (insn >> 0) & 0xF; /* 3:0 */
13305 /* Require 11:8 == 0 for Rn +/- Rm cases */
13316 if (rM == 15) goto after_load_store_sbyte_or_hword;
13323 if (rM == 15) goto after_load_store_sbyte_or_hword;
13325 if (rN == rM) goto after_load_store_sbyte_or_hword;
13349 eaE = mk_EA_reg_plusminus_reg( rN, bU, rM, dis_buf );
13592 UInt rM = INSN(3,0);
13593 // we don't decode the case (link && rM == 15), as that's
13595 if (!(link && rM == 15)) {
13599 // rM contains an interworking address exactly as we require
13602 assign( dst, getIRegA(rM) );
13609 : (rM == 14 ? Ijk_Ret : Ijk_Boring);
13612 DIP("b%sx r%u\n", link ? "l" : "", rM);
13614 DIP("b%sx%s r%u\n", link ? "l" : "", nCC(INSN_COND), rM);
13618 /* else: (link && rM == 15): just fall through */
13632 UInt rM = INSN(3,0);
13635 assign(arg, getIRegA(rM));
13643 DIP("clz%s r%u, r%u\n", nCC(INSN_COND), rD, rM);
13655 UInt rM = INSN(3,0);
13656 if (rD == 15 || rM == 15 || rS == 15) {
13664 assign( argL, getIRegA(rM));
13683 bitS ? 's' : ' ', nCC(INSN_COND), rD, rM, rS);
13695 UInt rM = INSN(11,8);
13697 if (rD == 15 || rM == 15 || rN == 15) {
13704 assign(argR, getIRegA(rM));
13707 DIP("sdiv r%u, r%u, r%u\n", rD, rN, rM);
13717 UInt rM = INSN(11,8);
13719 if (rD == 15 || rM == 15 || rN == 15) {
13726 assign(argR, getIRegA(rM));
13729 DIP("udiv r%u, r%u, r%u\n", rD, rN, rM);
13742 UInt rM = INSN(3,0);
13748 if (rD == 15 || rM == 15 || rS == 15 || rN == 15) {
13757 assign( argL, getIRegA(rM));
13781 nCC(INSN_COND), rD, rM, rS, rN);
13794 UInt rM = INSN(3,0);
13796 if (rDhi == 15 || rDlo == 15 || rM == 15 || rS == 15 || rDhi == rDlo) {
13807 assign( argL, getIRegA(rM));
13830 nCC(INSN_COND), rDlo, rDhi, rM, rS);
13843 UInt rM = INSN(3,0);
13845 if (rDhi == 15 || rDlo == 15 || rM == 15 || rS == 15 || rDhi == rDlo) {
13857 assign( argL, getIRegA(rM));
13883 rDlo, rDhi, rM, rS);
13967 UInt rM = INSN(3,0);
13974 if (rD == 15 || rN == 15 || rM == 15 || rN == rM || rN == rD) {
13984 assign(tNew, getIRegA(rM));
14007 isB ? "b" : "", nCC(INSN_COND), rD, rM, rN);
14175 UInt rM = INSN(3,0);
14181 assign(srcT, getIRegA(rM));
14228 DIP("%s%s r%u, r%u, ROR #%u\n", nm, nCC(INSN_COND), rD, rM, rot);
14320 A5-38 1 | 32 cond 0001 U000 Rn Rd 0000 11S1 Rm
14322 A5-42 2 | 32 cond 0001 U010 Rn Rd 0000 11S1 Rm
14324 A5-46 3 | 32 cond 0000 U000 Rn Rd 0000 11S1 Rm
14332 32 Rn +/- Rm
14366 UInt rM = (insn >> 0) & 0xF; /* 3:0 */
14375 /* Require 11:8 == 0 for Rn +/- Rm cases */
14386 if (rM == 15) goto after_load_store_doubleword;
14394 if (rM == 15) goto after_load_store_doubleword;
14396 if (rN == rM) goto after_load_store_doubleword;
14421 eaE = mk_EA_reg_plusminus_reg( rN, bU, rM, dis_buf );
14498 UInt rM = INSN(3,0);
14501 if (rN == 15/*it's {S,U}XTB*/ || rD == 15 || rM == 15) {
14507 assign(srcR, getIRegA(rM));
14516 isU ? 'u' : 's', nCC(INSN_COND), rD, rN, rM, rot);
14528 UInt rM = INSN(3,0);
14531 if (rN == 15/*it's {S,U}XTH*/ || rD == 15 || rM == 15) {
14537 assign(srcR, getIRegA(rM));
14547 isU ? 'u' : 's', nCC(INSN_COND), rD, rN, rM, rot);
14557 UInt rM = INSN(3,0);
14559 if (rM != 15 && rD != 15) {
14561 assign(rMt, getIRegA(rM));
14565 nCC(INSN_COND), rD, rM);
14573 UInt rM = INSN(3,0);
14574 if (rD != 15 && rM != 15) {
14576 assign(arg, getIRegA(rM));
14579 DIP("rbit r%u, r%u\n", rD, rM);
14590 UInt rM = INSN(11,8);
14592 if (rD != 15 && rM != 15 && rN != 15) {
14596 binop(Iop_MullS32, getIRegA(rN), getIRegA(rM)),
14600 nCC(INSN_COND), bitR ? "r" : "", rD, rN, rM);
14612 UInt rM = INSN(11,8);
14614 if (rD != 15 && rM != 15 && rN != 15) {
14620 binop(Iop_MullS32, getIRegA(rN), getIRegA(rM))),
14624 nCC(INSN_COND), bitR ? "r" : "", rD, rN, rM, rA);
15284 /* ---------------- CMP Rn, Rm ---------------- */
15287 UInt rM = INSN0(5,3);
15291 assign( argR, getIRegT(rM) );
15295 DIP("%s r%u, r%u\n", isCMN ? "cmn" : "cmp", rN, rM);
15300 /* ---------------- TST Rn, Rm ---------------- */
15302 UInt rM = INSN0(5,3);
15308 assign( res, binop(Iop_And32, getIRegT(rN), getIRegT(rM)) );
15311 DIP("tst r%u, r%u\n", rN, rM);
15316 /* ---------------- NEGS Rd, Rm ---------------- */
15317 /* Rd = -Rm */
15318 UInt rM = INSN0(5,3);
15322 assign(arg, getIRegT(rM));
15327 DIP("negs r%u, r%u\n", rD, rM);
15332 /* ---------------- MVNS Rd, Rm ---------------- */
15333 /* Rd = ~Rm */
15334 UInt rM = INSN0(5,3);
15341 assign(res, unop(Iop_Not32, getIRegT(rM)));
15346 DIP("mvns r%u, r%u\n", rD, rM);
15351 /* ---------------- ORRS Rd, Rm ---------------- */
15354 /* ---------------- ANDS Rd, Rm ---------------- */
15357 /* ---------------- EORS Rd, Rm ---------------- */
15360 /* ---------------- MULS Rd, Rm ---------------- */
15363 /* Rd = Rd `op` Rm */
15364 UInt rM = INSN0(5,3);
15371 assign( res, binop(anOp, getIRegT(rD), getIRegT(rM) ));
15377 DIP("%s r%u, r%u\n", anOpNm, rD, rM);
15382 /* ---------------- BICS Rd, Rm ---------------- */
15383 /* Rd = Rd & ~Rm */
15384 UInt rM = INSN0(5,3);
15392 rM) )));
15398 DIP("bics r%u, r%u\n", rD, rM);
15403 /* ---------------- ADCS Rd, Rm ---------------- */
15404 /* Rd = Rd + Rm + oldC */
15405 UInt rM = INSN0(5,3);
15412 assign(argR, getIRegT(rM));
15421 DIP("adcs r%u, r%u\n", rD, rM);
15426 /* ---------------- SBCS Rd, Rm ---------------- */
15427 /* Rd = Rd - Rm - (oldC ^ 1) */
15428 UInt rM = INSN0(5,3);
15435 assign(argR, getIRegT(rM));
15444 DIP("sbcs r%u, r%u\n", rD, rM);
15449 /* ---------------- UXTB Rd, Rm ---------------- */
15450 /* Rd = 8Uto32(Rm) */
15451 UInt rM = INSN0(5,3);
15453 putIRegT(rD, binop(Iop_And32, getIRegT(rM), mkU32(0xFF)),
15455 DIP("uxtb r%u, r%u\n", rD, rM);
15460 /* ---------------- SXTB Rd, Rm ---------------- */
15461 /* Rd = 8Sto32(Rm) */
15462 UInt rM = INSN0(5,3);
15465 binop(Iop_Shl32, getIRegT(rM), mkU8(24)),
15468 DIP("sxtb r%u, r%u\n", rD, rM);
15473 /* ---------------- UXTH Rd, Rm ---------------- */
15474 /* Rd = 16Uto32(Rm) */
15475 UInt rM = INSN0(5,3);
15477 putIRegT(rD, binop(Iop_And32, getIRegT(rM), mkU32(0xFFFF)),
15479 DIP("uxth r%u, r%u\n", rD, rM);
15484 /* ---------------- SXTH Rd, Rm ---------------- */
15485 /* Rd = 16Sto32(Rm) */
15486 UInt rM = INSN0(5,3);
15489 binop(Iop_Shl32, getIRegT(rM), mkU8(16)),
15492 DIP("sxth r%u, r%u\n", rD, rM);
15555 /* ---------------- REV Rd, Rm ---------------- */
15556 /* ---------------- REV16 Rd, Rm ---------------- */
15557 UInt rM = INSN0(5,3);
15561 assign(arg, getIRegT(rM));
15564 DIP("rev%s r%u, r%u\n", isREV ? "" : "16", rD, rM);
15597 /* ---------------- BX rM ---------------- */
15601 UInt rM = (INSN0(6,6) << 3) | INSN0(5,3);
15608 if (rM <= 14) {
15609 assign( dst, getIRegT(rM) );
15611 vassert(rM == 15);
15615 dres.jk_StopHere = rM == 14 ? Ijk_Ret : Ijk_Boring;
15617 DIP("bx r%u (possibly switch to ARM mode)\n", rM);
15623 /* ---------------- BLX rM ---------------- */
15624 /* Branch and link to interworking address in rM. */
15627 UInt rM = (INSN0(6,6) << 3) | INSN0(5,3);
15629 if (rM <= 14) {
15635 assign( dst, getIRegT(rM) );
15641 DIP("blx r%u (possibly switch to ARM mode)\n", rM);
15682 /* ---------------- ADD(HI) Rd, Rm ---------------- */
15685 UInt rM = (h2 << 3) | INSN0(5,3);
15688 if (rD == 15 && rM == 15) {
15692 assign( res, binop(Iop_Add32, getIRegT(rD), getIRegT(rM) ));
15707 DIP("add(hi) r%u, r%u\n", rD, rM);
15714 /* ---------------- CMP(HI) Rd, Rm ---------------- */
15717 UInt rM = (h2 << 3) | INSN0(5,3);
15723 assign( argR, getIRegT(rM) );
15726 DIP("cmphi r%u, r%u\n", rN, rM);
15733 /* ---------------- MOV(HI) Rd, Rm ---------------- */
15736 UInt rM = (h2 << 3) | INSN0(5,3);
15739 Rm are "low" registers, but newer versions allow it. */
15742 assign( val, getIRegT(rM) );
15754 dres.jk_StopHere = rM == 14 ? Ijk_Ret : Ijk_Boring;
15757 DIP("mov r%u, r%u\n", rD, rM);
15993 /* ---------------- ADDS Rd, Rn, Rm ---------------- */
15994 /* ---------------- SUBS Rd, Rn, Rm ---------------- */
15995 UInt rM = INSN0(8,6);
16002 assign( argR, getIRegT(rM) );
16008 DIP("%s r%u, r%u, r%u\n", isSub ? "subs" : "adds", rD, rN, rM);
16014 /* ------------- LDR Rd, [Rn, Rm] ------------- */
16015 /* ------------- STR Rd, [Rn, Rm] ------------- */
16016 /* LDR/STR Rd, [Rn + Rm] */
16019 UInt rM = INSN0(8,6);
16026 IRExpr* ea = binop(Iop_Add32, getIRegT(rN), getIRegT(rM));
16035 DIP("%s r%u, [r%u, r%u]\n", isLD ? "ldr" : "str", rD, rN, rM);
16041 /* ------------- LDRH Rd, [Rn, Rm] ------------- */
16042 /* ------------- STRH Rd, [Rn, Rm] ------------- */
16043 /* LDRH/STRH Rd, [Rn + Rm] */
16046 UInt rM = INSN0(8,6);
16053 IRExpr* ea = binop(Iop_Add32, getIRegT(rN), getIRegT(rM));
16063 DIP("%sh r%u, [r%u, r%u]\n", isLD ? "ldr" : "str", rD, rN, rM);
16068 /* ------------- LDRSH Rd, [Rn, Rm] ------------- */
16069 /* LDRSH Rd, [Rn + Rm] */
16072 UInt rM = INSN0(8,6);
16078 IRExpr* ea = binop(Iop_Add32, getIRegT(rN), getIRegT(rM));
16084 DIP("ldrsh r%u, [r%u, r%u]\n", rD, rN, rM);
16089 /* ------------- LDRSB Rd, [Rn, Rm] ------------- */
16090 /* LDRSB Rd, [Rn + Rm] */
16093 UInt rM = INSN0(8,6);
16099 IRExpr* ea = binop(Iop_Add32, getIRegT(rN), getIRegT(rM));
16105 DIP("ldrsb r%u, [r%u, r%u]\n", rD, rN, rM);
16111 /* ------------- LDRB Rd, [Rn, Rm] ------------- */
16112 /* ------------- STRB Rd, [Rn, Rm] ------------- */
16113 /* LDRB/STRB Rd, [Rn + Rm] */
16116 UInt rM = INSN0(8,6);
16123 IRExpr* ea = binop(Iop_Add32, getIRegT(rN), getIRegT(rM));
16133 DIP("%sb r%u, [r%u, r%u]\n", isLD ? "ldr" : "str", rD, rN, rM);
16448 /* ---------------- LSLS Rd, Rm, #imm5 ---------------- */
16449 /* ---------------- LSRS Rd, Rm, #imm5 ---------------- */
16450 /* ---------------- ASRS Rd, Rm, #imm5 ---------------- */
16452 UInt rM = INSN0(5,3);
16459 assign(rMt, getIRegT(rM));
16466 dis_buf, &res, &resC, rMt, imm5, rM
16472 dis_buf, &res, &resC, rMt, imm5, rM
16478 dis_buf, &res, &resC, rMt, imm5, rM
16490 DIP("%ss r%u, r%u, #%u\n", wot, rD, rM, imm5);
16979 /* ---------- (T3) ADD{S}.W Rd, Rn, Rm, {shift} ---------- */
16980 /* ---------- (T3) SUB{S}.W Rd, Rn, Rm, {shift} ---------- */
16981 /* ---------- (T3) RSB{S}.W Rd, Rn, Rm, {shift} ---------- */
16989 UInt rM = INSN1(3,0);
16994 Bool valid = !isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM);
17023 assign(rMt, getIRegT(rM));
17027 dis_buf, &argR, NULL, rMt, how, imm5, rM
17058 /* ---------- (T3) ADC{S}.W Rd, Rn, Rm, {shift} ---------- */
17059 /* ---------- (T2) SBC{S}.W Rd, Rn, Rm, {shift} ---------- */
17068 UInt rM = INSN1(3,0);
17069 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
17078 assign(rMt, getIRegT(rM));
17085 dis_buf, &argR, NULL, rMt, how, imm5, rM
17123 /* ---------- (T3) AND{S}.W Rd, Rn, Rm, {shift} ---------- */
17124 /* ---------- (T3) ORR{S}.W Rd, Rn, Rm, {shift} ---------- */
17125 /* ---------- (T3) EOR{S}.W Rd, Rn, Rm, {shift} ---------- */
17126 /* ---------- (T3) BIC{S}.W Rd, Rn, Rm, {shift} ---------- */
17127 /* ---------- (T1) ORN{S}.W Rd, Rn, Rm, {shift} ---------- */
17137 UInt rM = INSN1(3,0);
17138 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
17160 assign(rMt, getIRegT(rM));
17166 dis_buf, &argR, bS ? &oldC : NULL, rMt, how, imm5, rM
17192 /* -------------- (T?) LSL{S}.W Rd, Rn, Rm -------------- */
17193 /* -------------- (T?) LSR{S}.W Rd, Rn, Rm -------------- */
17194 /* -------------- (T?) ASR{S}.W Rd, Rn, Rm -------------- */
17195 /* -------------- (T?) ROR{S}.W Rd, Rn, Rm -------------- */
17202 UInt rM = INSN1(3,0);
17204 Bool valid = !isBadRegT(rN) && !isBadRegT(rM) && !isBadRegT(rD);
17214 assign(rMt, getIRegT(rM));
17217 rM
17227 nm, bS ? "s" : "", rD, rN, rM);
17269 /* -------------- (T?) TST.W Rn, Rm, {shift} -------------- */
17270 /* -------------- (T?) TEQ.W Rn, Rm, {shift} -------------- */
17277 UInt rM = INSN1(3,0);
17278 if (!isBadRegT(rN) && !isBadRegT(rM)) {
17288 assign(rMt, getIRegT(rM));
17293 dis_buf, &argR, &oldC, rMt, how, imm5, rM
17310 /* -------------- (T3) CMP.W Rn, Rm, {shift} -------------- */
17311 /* -------------- (T2) CMN.W Rn, Rm, {shift} -------------- */
17318 UInt rM = INSN1(3,0);
17319 if (!isBadRegT(rN) && !isBadRegT(rM)) {
17328 assign(rMt, getIRegT(rM));
17332 dis_buf, &argR, NULL, rMt, how, imm5, rM
17595 op Rt, [Rn, Rm, LSL #imm8]
17630 UInt rM = INSN1(3,0);
17638 if (rN == 15 || isBadRegT(rT) || isBadRegT(rM))
17642 if (rN == 15 || isBadRegT(rM))
17666 binop(Iop_Shl32, getIRegT(rM), mkU8(imm2)) ));
17725 nm, rT, rN, rM, imm2);
18033 UInt rM = INSN1(3,0);
18035 if (bH/*ATC*/ || (rN != 13 && !isBadRegT(rM))) {
18045 bH ? binop(Iop_Shl32, getIRegT(rM), mkU8(1))
18046 : getIRegT(rM));
18067 bH ? 'h' : 'b', rN, rM, bH ? ", LSL #1" : "");
18127 UInt rM = INSN1(3,0);
18129 if (!isBadRegT(rD) && !isBadRegT(rM)) {
18134 assign(srcT, getIRegT(rM));
18186 DIP("%s r%u, r%u, ror #%u\n", nm, rD, rM, 8 * rot);
18191 /* -------------- MUL.W Rd, Rn, Rm -------------- */
18196 UInt rM = INSN1(3,0);
18197 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
18199 assign(res, binop(Iop_Mul32, getIRegT(rN), getIRegT(rM)));
18201 DIP("mul.w r%u, r%u, r%u\n", rD, rN, rM);
18206 /* -------------- SDIV.W Rd, Rn, Rm -------------- */
18211 UInt rM = INSN1(3,0);
18212 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
18217 assign(argR, getIRegT(rM));
18220 DIP("sdiv.w r%u, r%u, r%u\n", rD, rN, rM);
18225 /* -------------- UDIV.W Rd, Rn, Rm -------------- */
18230 UInt rM = INSN1(3,0);
18231 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
18236 assign(argR, getIRegT(rM));
18239 DIP("udiv.w r%u, r%u, r%u\n", rD, rN, rM);
18251 UInt rM = INSN1(3,0);
18253 && !isBadRegT(rN) && !isBadRegT(rM) && rDlo != rDhi) {
18256 getIRegT(rN), getIRegT(rM)));
18260 isU ? 'u' : 's', rDlo, rDhi, rN, rM);
18272 UInt rM = INSN1(3,0);
18274 && !isBadRegT(rM) && !isBadRegT(rA)) {
18280 binop(Iop_Mul32, getIRegT(rN), getIRegT(rM))));
18283 isMLA ? "mla" : "mls", rD, rN, rM, rA);
18313 UInt rM = INSN1(3,0);
18315 && !isBadRegT(rM) && rDhi != rDlo) {
18324 assign( argL, getIRegT(rM));
18335 isS ? 's' : 'u', rDlo, rDhi, rN, rM);
18409 UInt rM = INSN1(3,0);
18411 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
18415 assign(srcR, getIRegT(rM));
18424 isU ? 'u' : 's', rD, rN, rM, rot);
18438 UInt rM = INSN1(3,0);
18440 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
18444 assign(srcR, getIRegT(rM));
18453 isU ? 'u' : 's', rD, rN, rM, rot);
18762 UInt rM = INSN1(3,0);
18765 if (!isBadRegT(rM)) {
18766 DIP("pld%s [r%u, r%u, lsl %d]\n", bW ? "w" : "", rN, rM, imm2);
18814 UInt rM = INSN1(3,0);
18816 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
18820 binop(Iop_MullS32, getIRegT(rN), getIRegT(rM)),
18824 bitR ? "r" : "", rD, rN, rM);
18836 UInt rM = INSN1(3,0);
18838 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM) && (rA != 13)) {
18844 binop(Iop_MullS32, getIRegT(rN), getIRegT(rM))),
18848 bitR ? "r" : "", rD, rN, rM, rA);
