Lines Matching refs:r12
166 // r12 is used as a spill/reload temporary
173 // and r12 dedicated as a spill temporary.
1623 vex_printf("movw r12,0x%x; ",
1625 vex_printf("movt r12,0x%x; ",
1627 vex_printf("str r12,");
1629 vex_printf("; movw r12,LO16($disp_cp_chain_me_to_%sEP); ",
1631 vex_printf("movt r12,HI16($disp_cp_chain_me_to_%sEP); ",
1633 vex_printf("blx r12 }");
1643 vex_printf("; movw r12,LO16($disp_cp_xindir); ");
1644 vex_printf("movt r12,HI16($disp_cp_xindir); ");
1645 vex_printf("blx r12 }");
1657 vex_printf("movw r12,LO16($disp_cp_xassisted); ");
1658 vex_printf("movt r12,HI16($disp_cp_xassisted); ");
1659 vex_printf("blx r12 }");
1960 vex_printf("(evCheck) ldr r12,");
1962 vex_printf("; subs r12,r12,$1; str r12,");
1964 vex_printf("; bpl nofail; ldr r12,");
1966 vex_printf("; bx r12; nofail:");
1969 vex_printf("(profInc) movw r12,LO16($NotKnownYet); "
1970 "movw r12,HI16($NotKnownYet); "
1971 "ldr r11,[r12]; "
1973 "str r11,[r12]; "
1974 "ldr r11,[r12+4]; "
1976 "str r11,[r12+4]");
2473 /* hardwires r11 and r12 -- nothing to modify. */
2549 HReg r12 = hregARM_R12(); /* spill temp */
2554 /* r12 = r8 + (1024 * offsetKB) */
2555 *i1 = ARMInstr_Alu(ARMalu_ADD, r12, r8,
2558 base = r12;
2574 HReg r12 = hregARM_R12();
2575 *i1 = ARMInstr_Add32(r12, r8, offsetB);
2576 *i2 = ARMInstr_NLdStQ(False, rreg, mkARMAModeN_R(r12));
2604 HReg r12 = hregARM_R12(); /* spill temp */
2609 /* r12 = r8 + (1024 * offsetKB) */
2610 *i1 = ARMInstr_Alu(ARMalu_ADD, r12, r8,
2613 base = r12;
2629 HReg r12 = hregARM_R12();
2630 *i1 = ARMInstr_Add32(r12, r8, offsetB);
2631 *i2 = ARMInstr_NLdStQ(True, rreg, mkARMAModeN_R(r12));
3148 /* movw r12, lo16(dstGA) */
3149 /* movt r12, hi16(dstGA) */
3150 /* str r12, amR15T */
3160 /* movw r12, lo16(VG_(disp_cp_chain_me_to_{slowEP,fastEP})) */
3161 /* movt r12, hi16(VG_(disp_cp_chain_me_to_{slowEP,fastEP})) */
3162 /* blx r12 (A1) */
3211 /* movw r12, lo16(VG_(disp_cp_xindir)) */
3212 /* movt r12, hi16(VG_(disp_cp_xindir)) */
3213 /* bx r12 (A1) */
3276 /* movw r12, lo16(VG_(disp_cp_xassisted)) */
3277 /* movt r12, hi16(VG_(disp_cp_xassisted)) */
3278 /* bx r12 (A1) */
4467 ldr r12, [r8 + #4] 4 == offsetof(host_EvC_COUNTER)
4468 subs r12, r12, #1 (A1)
4469 str r12, [r8 + #4] 4 == offsetof(host_EvC_COUNTER)
4471 ldr r12, [r8 + #0] 0 == offsetof(host_EvC_FAILADDR)
4472 bx r12
4478 *p++ = 0xE25CC001; /* subs r12, r12, #1 */
4484 *p++ = 0xE12FFF1C; /* bx r12 */
4498 movw r12, lo16(0x65556555)
4499 movt r12, lo16(0x65556555)
4500 ldr r11, [r12]
4502 str r11, [r12]
4503 ldr r11, [r12+4]
4505 str r11, [r12+4]
4552 movw r12, lo16(disp_cp_chain_me_to_EXPECTED)
4553 movt r12, hi16(disp_cp_chain_me_to_EXPECTED)
4554 blx r12
4566 movw r12, lo16(place_to_jump_to)
4567 movt r12, hi16(place_to_jump_to)
4568 bx r12
4633 movw r12, lo16(place_to_jump_to_EXPECTED)
4634 movt r12, lo16(place_to_jump_to_EXPECTED)
4635 bx r12
4671 movw r12, lo16(disp_cp_chain_me)
4672 movt r12, hi16(disp_cp_chain_me)
4673 blx r12
