Lines Matching refs:dmsg
47 VG_(dmsg)("warning: Pentium 4 with %d KB micro-op instruction trace cache\n",
49 VG_(dmsg)(" Simulating a %d KB I-cache with %d B lines\n",
81 VG_(dmsg)("warning: CPUID level < 2 for Intel processor (%d)\n", level);
97 VG_(dmsg)("warning: non-zero CPUID trials for Intel processor (%d)\n",
266 case 3: VG_(dmsg)("warning: L1 unified cache ignored\n"); break;
267 default: VG_(dmsg)("warning: L1 cache of unknown type ignored\n"); break;
273 case 1: VG_(dmsg)("warning: L2 data cache ignored\n"); break;
274 case 2: VG_(dmsg)("warning: L2 instruction cache ignored\n"); break;
276 default: VG_(dmsg)("warning: L2 cache of unknown type ignored\n"); break;
282 case 1: VG_(dmsg)("warning: L3 data cache ignored\n"); break;
283 case 2: VG_(dmsg)("warning: L3 instruction cache ignored\n"); break;
285 default: VG_(dmsg)("warning: L3 cache of unknown type ignored\n"); break;
289 VG_(dmsg)("warning: L%u cache ignored\n", (info[0] & 0xe0) >> 5);
299 VG_(dmsg)("warning: Unknown Intel cache config value (0x%x), ignoring\n",
307 VG_(dmsg)("warning: L3 cache found, using its data for the LL simulation.\n");
313 VG_(dmsg)("warning: L2 cache not installed, ignore LL results.\n");
375 VG_(dmsg)("warning: ext_level < 0x80000006 for AMD processor (0x%x)\n",
387 VG_(dmsg)("warning: Buggy Duron stepping A0. Assuming L2 size=65536 bytes\n");
411 VG_(dmsg)("warning: L3 cache found, using its data for the L2 simulation.\n");
424 VG_(dmsg)("CPUID instruction not supported\n");
433 VG_(dmsg)("CPUID level is 0, early Pentium?\n");
458 VG_(dmsg)("CPU vendor ID not recognised (%s)\n", vendor_id);
514 VG_(dmsg)("warning: pretending that LL cache has associativity"
539 VG_(dmsg)("Warning: Couldn't auto-detect cache config, using one "
