Lines Matching refs:regT0
55 emitLoad(src, regT1, regT0);
58 addSlowCase(branchTest32(Zero, regT0, TrustedImm32(0x7fffffff)));
59 neg32(regT0);
60 emitStoreInt32(dst, regT0, (dst == src));
70 store32(regT0, payloadFor(dst));
83 stubCall.addArgument(regT1, regT0);
98 emitLoad(op2, regT1, regT0);
101 emitLoadCharacterString(regT0, regT0, failures);
103 addJump(branch32(LessThanOrEqual, regT0, Imm32(asString(getConstantOperand(op1))->tryGetValue()[0])), target);
107 emitLoad(op1, regT1, regT0);
110 emitLoadCharacterString(regT0, regT0, failures);
112 addJump(branch32(GreaterThanOrEqual, regT0, Imm32(asString(getConstantOperand(op2))->tryGetValue()[0])), target);
121 emitLoad(op1, regT1, regT0);
123 addJump(branch32(GreaterThanOrEqual, regT0, Imm32(getConstantOperand(op2).asInt32())), target);
125 emitLoad2(op1, regT1, regT0, op2, regT3, regT2);
128 addJump(branch32(GreaterThanOrEqual, regT0, regT2), target);
173 emitJumpSlowToHot(branchTest32(Zero, regT0), target);
187 emitLoad(op2, regT1, regT0);
190 emitLoadCharacterString(regT0, regT0, failures);
192 addJump(branch32(GreaterThan, regT0, Imm32(asString(getConstantOperand(op1))->tryGetValue()[0])), target);
196 emitLoad(op1, regT1, regT0);
199 emitLoadCharacterString(regT0, regT0, failures);
201 addJump(branch32(LessThan, regT0, Imm32(asString(getConstantOperand(op2))->tryGetValue()[0])), target);
209 emitLoad(op1, regT1, regT0);
211 addJump(branch32(LessThan, regT0, Imm32(getConstantOperand(op2).asInt32())), target);
213 emitLoad2(op1, regT1, regT0, op2, regT3, regT2);
216 addJump(branch32(LessThan, regT0, regT2), target);
260 emitJumpSlowToHot(branchTest32(NonZero, regT0), target);
274 emitLoad(op2, regT1, regT0);
277 emitLoadCharacterString(regT0, regT0, failures);
279 addJump(branch32(invert ? LessThan : GreaterThanOrEqual, regT0, Imm32(asString(getConstantOperand(op1))->tryGetValue()[0])), target);
283 emitLoad(op1, regT1, regT0);
286 emitLoadCharacterString(regT0, regT0, failures);
288 addJump(branch32(invert ? GreaterThan : LessThanOrEqual, regT0, Imm32(asString(getConstantOperand(op2))->tryGetValue()[0])), target);
296 emitLoad(op1, regT1, regT0);
298 addJump(branch32(invert ? GreaterThan : LessThanOrEqual, regT0, Imm32(getConstantOperand(op2).asInt32())), target);
300 emitLoad2(op1, regT1, regT0, op2, regT3, regT2);
303 addJump(branch32(invert ? GreaterThan : LessThanOrEqual, regT0, regT2), target);
348 emitJumpSlowToHot(branchTest32(invert ? Zero : NonZero, regT0), target);
370 emitLoad(op1, regT1, regT0);
372 lshift32(Imm32(getConstantOperand(op2).asInt32()), regT0);
373 emitStoreInt32(dst, regT0, dst == op1);
377 emitLoad2(op1, regT1, regT0, op2, regT3, regT2);
381 lshift32(regT2, regT0);
382 emitStoreInt32(dst, regT0, dst == op1 || dst == op2);
412 emitLoad(op1, regT1, regT0);
417 urshift32(Imm32(shift & 0x1f), regT0);
422 addSlowCase(branch32(LessThan, regT0, TrustedImm32(0)));
424 rshift32(Imm32(shift & 0x1f), regT0);
426 emitStoreInt32(dst, regT0, dst == op1);
430 emitLoad2(op1, regT1, regT0, op2, regT3, regT2);
435 urshift32(regT2, regT0);
436 addSlowCase(branch32(LessThan, regT0, TrustedImm32(0)));
438 rshift32(regT2, regT0);
439 emitStoreInt32(dst, regT0, dst == op1 || dst == op2);
449 // op1 = regT1:regT0
455 failures.append(branchTruncateDoubleToInt32(fpRegT0, regT0));
458 urshift32(Imm32(shift & 0x1f), regT0);
460 failures.append(branch32(LessThan, regT0, TrustedImm32(0)));
462 rshift32(Imm32(shift & 0x1f), regT0);
463 emitStoreInt32(dst, regT0, false);
470 // op1 = regT1:regT0
478 Jump cantTruncate = branchTruncateDoubleToInt32(fpRegT0, regT0);
480 urshift32(regT2, regT0);
482 rshift32(regT2, regT0);
483 emitStoreInt32(dst, regT0, false);
537 emitLoad(op, regT1, regT0);
539 and32(Imm32(constant), regT0);
540 emitStoreInt32(dst, regT0, (op == dst));
544 emitLoad2(op1, regT1, regT0, op2, regT3, regT2);
547 and32(regT2, regT0);
548 emitStoreInt32(dst, regT0, (op1 == dst || op2 == dst));
578 emitLoad(op, regT1, regT0);
580 or32(Imm32(constant), regT0);
581 emitStoreInt32(dst, regT0, (op == dst));
585 emitLoad2(op1, regT1, regT0, op2, regT3, regT2);
588 or32(regT2, regT0);
589 emitStoreInt32(dst, regT0, (op1 == dst || op2 == dst));
619 emitLoad(op, regT1, regT0);
621 xor32(Imm32(constant), regT0);
622 emitStoreInt32(dst, regT0, (op == dst));
626 emitLoad2(op1, regT1, regT0, op2, regT3, regT2);
629 xor32(regT2, regT0);
630 emitStoreInt32(dst, regT0, (op1 == dst || op2 == dst));
656 emitLoad(src, regT1, regT0);
659 not32(regT0);
660 emitStoreInt32(dst, regT0, (dst == src));
670 stubCall.addArgument(regT1, regT0);
681 emitLoad(srcDst, regT1, regT0);
687 emitStoreInt32(dst, regT0);
689 addSlowCase(branchAdd32(Overflow, TrustedImm32(1), regT0));
690 emitStoreInt32(srcDst, regT0, true);
715 emitLoad(srcDst, regT1, regT0);
721 emitStoreInt32(dst, regT0);
723 addSlowCase(branchSub32(Overflow, TrustedImm32(1), regT0));
724 emitStoreInt32(srcDst, regT0, true);
748 emitLoad(srcDst, regT1, regT0);
751 addSlowCase(branchAdd32(Overflow, TrustedImm32(1), regT0));
752 emitStoreInt32(srcDst, regT0, true);
773 emitLoad(srcDst, regT1, regT0);
776 addSlowCase(branchSub32(Overflow, TrustedImm32(1), regT0));
777 emitStoreInt32(srcDst, regT0, true);
819 emitLoad2(op1, regT1, regT0, op2, regT3, regT2);
824 addSlowCase(branchAdd32(Overflow, regT2, regT0));
825 emitStoreInt32(dst, regT0, (op1 == dst || op2 == dst));
842 emitLoad(op, regT1, regT0);
844 addSlowCase(branchAdd32(Overflow, Imm32(constant), regT0));
845 emitStoreInt32(dst, regT0, (op == dst));
928 emitLoad2(op1, regT1, regT0, op2, regT3, regT2);
933 addSlowCase(branchSub32(Overflow, regT2, regT0));
934 emitStoreInt32(dst, regT0, (op1 == dst || op2 == dst));
951 emitLoad(op, regT1, regT0);
953 addSlowCase(branchSub32(Overflow, Imm32(constant), regT0));
954 emitStoreInt32(dst, regT0, (op == dst));
1093 emitLoadPayload(op1, regT0);
1095 convertInt32ToDouble(regT0, fpRegT0);
1159 emitLoad2(op1, regT1, regT0, op2, regT3, regT2);
1164 move(regT0, regT3);
1165 addSlowCase(branchMul32(Overflow, regT2, regT0));
1166 addSlowCase(branchTest32(Zero, regT0));
1167 emitStoreInt32(dst, regT0, (op1 == dst || op2 == dst));
1241 emitLoad2(op1, regT1, regT0, op2, regT3, regT2);
1246 convertInt32ToDouble(regT0, fpRegT0);
1251 branchConvertDoubleToInt32(fpRegT0, regT0, doubleResult, fpRegT1);
1254 emitStoreInt32(dst, regT0, (op1 == dst || op2 == dst));
1306 ASSERT(regT0 == X86Registers::eax);
1313 emitLoad(op1, regT1, regT0);
1317 addSlowCase(branch32(Equal, regT0, TrustedImm32(0x80000000))); // -2147483648 / -1 => EXC_ARITHMETIC
1319 emitLoad2(op1, regT1, regT0, op2, regT3, regT2);
1323 addSlowCase(branch32(Equal, regT0, TrustedImm32(0x80000000))); // -2147483648 / -1 => EXC_ARITHMETIC
1327 move(regT0, regT3); // Save dividend payload, in case of 0.
1332 m_assembler.div(regT0, regT2);
1380 emitLoad2(op1, regT1, regT0, op2, regT3, regT2);
1388 emitStoreInt32(dst, regT0, (op1 == dst || op2 == dst));
