Lines Matching refs:regT2
117 emitLoad(op2, regT3, regT2);
119 addJump(branch32(LessThanOrEqual, regT2, Imm32(getConstantOperand(op1).asInt32())), target);
125 emitLoad2(op1, regT1, regT0, op2, regT3, regT2);
128 addJump(branch32(GreaterThanOrEqual, regT0, regT2), target);
205 emitLoad(op2, regT3, regT2);
207 addJump(branch32(GreaterThan, regT2, Imm32(getConstantOperand(op1).asInt32())), target);
213 emitLoad2(op1, regT1, regT0, op2, regT3, regT2);
216 addJump(branch32(LessThan, regT0, regT2), target);
292 emitLoad(op2, regT3, regT2);
294 addJump(branch32(invert ? LessThan : GreaterThanOrEqual, regT2, Imm32(getConstantOperand(op1).asInt32())), target);
300 emitLoad2(op1, regT1, regT0, op2, regT3, regT2);
303 addJump(branch32(invert ? GreaterThan : LessThanOrEqual, regT0, regT2), target);
377 emitLoad2(op1, regT1, regT0, op2, regT3, regT2);
381 lshift32(regT2, regT0);
430 emitLoad2(op1, regT1, regT0, op2, regT3, regT2);
435 urshift32(regT2, regT0);
438 rshift32(regT2, regT0);
471 // op2 = regT3:regT2
480 urshift32(regT2, regT0);
482 rshift32(regT2, regT0);
544 emitLoad2(op1, regT1, regT0, op2, regT3, regT2);
547 and32(regT2, regT0);
585 emitLoad2(op1, regT1, regT0, op2, regT3, regT2);
588 or32(regT2, regT0);
626 emitLoad2(op1, regT1, regT0, op2, regT3, regT2);
629 xor32(regT2, regT0);
819 emitLoad2(op1, regT1, regT0, op2, regT3, regT2);
824 addSlowCase(branchAdd32(Overflow, regT2, regT0));
857 move(Imm32(constant), regT2);
858 convertInt32ToDouble(regT2, fpRegT0);
928 emitLoad2(op1, regT1, regT0, op2, regT3, regT2);
933 addSlowCase(branchSub32(Overflow, regT2, regT0));
966 move(Imm32(constant), regT2);
967 convertInt32ToDouble(regT2, fpRegT0);
1025 emitLoad(op2, regT3, regT2);
1032 convertInt32ToDouble(regT2, fpRegT0);
1159 emitLoad2(op1, regT1, regT0, op2, regT3, regT2);
1165 addSlowCase(branchMul32(Overflow, regT2, regT0));
1191 Jump negZero = branchOr32(Signed, regT2, regT3);
1241 emitLoad2(op1, regT1, regT0, op2, regT3, regT2);
1247 convertInt32ToDouble(regT2, fpRegT1);
1308 ASSERT(regT2 == X86Registers::ecx);
1314 move(Imm32(getConstantOperand(op2).asInt32()), regT2);
1319 emitLoad2(op1, regT1, regT0, op2, regT3, regT2);
1324 addSlowCase(branch32(Equal, regT2, TrustedImm32(0))); // divide by 0
1330 m_assembler.idivl_r(regT2);
1332 m_assembler.div(regT0, regT2);
1380 emitLoad2(op1, regT1, regT0, op2, regT3, regT2);
1384 addSlowCase(branch32(Equal, regT2, TrustedImm32(0)));
