Lines Matching refs:amode
230 amode.value = immediate;
236 amode.reg = Rm;
237 amode.stype = type;
238 amode.value = shift;
262 amode.value = immed12;
263 amode.writeback = W;
273 amode.value = immed12;
282 amode.reg = Rm;
283 // amode.stype = type; // more advanced modes not used in GGLAssembler yet
284 // amode.value = shift;
285 // amode.writeback = W;
315 amode.value = immed8;
322 amode.reg = Rm;
383 if ((!_signed && amode.value > 0xffff)
384 || (_signed && ((int)amode.value < -32768 || (int)amode.value > 32767) )) {
385 mMips->LUI(tmpReg, (amode.value >> 16));
386 if (amode.value & 0x0000ffff) {
387 mMips->ORI(tmpReg, tmpReg, (amode.value & 0x0000ffff));
392 source = amode.value;
396 switch (amode.stype) {
397 case LSL: mMips->SLL(tmpReg, amode.reg, amode.value); break;
398 case LSR: mMips->SRL(tmpReg, amode.reg, amode.value); break;
399 case ASR: mMips->SRA(tmpReg, amode.reg, amode.value); break;
401 mMips->ROTR(tmpReg, amode.reg, amode.value);
403 mMips->RORIsyn(tmpReg, amode.reg, amode.value);
498 if (amode.value > 0xffff) {
499 mMips->LUI(Rd, (amode.value >> 16));
500 if (amode.value & 0x0000ffff) {
501 mMips->ORI(Rd, Rd, (amode.value & 0x0000ffff));
504 mMips->ORI(Rd, 0, amode.value);
507 switch (amode.stype) {
508 case LSL: mMips->SLL(Rd, amode.reg, amode.value); break;
509 case LSR: mMips->SRL(Rd, amode.reg, amode.value); break;
510 case ASR: mMips->SRA(Rd, amode.reg, amode.value); break;
512 mMips->ROTR(Rd, amode.reg, amode.value);
514 mMips->RORIsyn(Rd, amode.reg, amode.value);
530 if (amode.value > 0xffff) {
531 mMips->LUI(Rd, (amode.value >> 16));
532 if (amode.value & 0x0000ffff) {
533 mMips->ORI(Rd, Rd, (amode.value & 0x0000ffff));
536 mMips->ORI(Rd, 0, amode.value);
539 switch (amode.stype) {
540 case LSL: mMips->SLL(Rd, amode.reg, amode.value); break;
541 case LSR: mMips->SRL(Rd, amode.reg, amode.value); break;
542 case ASR: mMips->SRA(Rd, amode.reg, amode.value); break;
544 amode.reg, amode.value);
546 mMips->RORIsyn(Rd, amode.reg, amode.value);
775 amode.value = 0;
776 amode.writeback = 0;
782 mMips->LW(Rd, Rn, amode.value);
783 if (amode.writeback) { // OPTIONAL writeback on pre-index mode
784 mMips->ADDIU(Rn, Rn, amode.value);
792 mMips->ADDIU(Rn, Rn, amode.value);
796 mMips->ADDU(R_at, Rn, amode.reg);
809 amode.value = 0;
810 amode.writeback = 0;
813 mMips->LBU(Rd, Rn, amode.value);
814 if (amode.writeback) { // OPTIONAL writeback on pre-index mode
815 mMips->ADDIU(Rn, Rn, amode.value);
820 mMips->ADDIU(Rn, Rn, amode.value);
824 mMips->ADDU(R_at, Rn, amode.reg);
838 amode.value = 0;
839 amode.writeback = 0;
845 if (amode.writeback) { // OPTIONAL writeback on pre-index mode
848 mMips->ADDIU(Rn, Rn, amode.value);
852 mMips->SW(Rd, Rn, amode.value);
857 mMips->ADDIU(Rn, Rn, amode.value); // post index always writes back
861 mMips->ADDU(R_at, Rn, amode.reg);
874 amode.value = 0;
875 amode.writeback = 0;
878 mMips->SB(Rd, Rn, amode.value);
879 if (amode.writeback) { // OPTIONAL writeback on pre-index mode
880 mMips->ADDIU(Rn, Rn, amode.value);
885 mMips->ADDIU(Rn, Rn, amode.value);
889 mMips->ADDU(R_at, Rn, amode.reg);
902 amode.value = 0;
905 mMips->LHU(Rd, Rn, amode.value);
909 mMips->ADDIU(Rn, Rn, amode.value);
913 if (amode.reg >= 0) {
914 mMips->ADDU(R_at, Rn, amode.reg);
916 mMips->SUBU(R_at, Rn, abs(amode.reg));
944 amode.value = 0;
947 mMips->SH(Rd, Rn, amode.value);
951 mMips->ADDIU(Rn, Rn, amode.value);
955 if (amode.reg >= 0) {
956 mMips->ADDU(R_at, Rn, amode.reg);
958 mMips->SUBU(R_at, Rn, abs(amode.reg));
