1 //===-- SIInstrInfo.h - SI Instruction Info Interface ---------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 /// \file 11 /// \brief Interface definition for SIInstrInfo. 12 // 13 //===----------------------------------------------------------------------===// 14 15 16 #ifndef SIINSTRINFO_H 17 #define SIINSTRINFO_H 18 19 #include "AMDGPUInstrInfo.h" 20 #include "SIRegisterInfo.h" 21 22 namespace llvm { 23 24 class SIInstrInfo : public AMDGPUInstrInfo { 25 private: 26 const SIRegisterInfo RI; 27 28 public: 29 explicit SIInstrInfo(AMDGPUTargetMachine &tm); 30 31 const SIRegisterInfo &getRegisterInfo() const; 32 33 virtual void copyPhysReg(MachineBasicBlock &MBB, 34 MachineBasicBlock::iterator MI, DebugLoc DL, 35 unsigned DestReg, unsigned SrcReg, 36 bool KillSrc) const; 37 38 virtual MachineInstr *commuteInstruction(MachineInstr *MI, 39 bool NewMI=false) const; 40 41 virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg, 42 int64_t Imm) const; 43 44 virtual unsigned getIEQOpcode() const { assert(!"Implement"); return 0;} 45 virtual bool isMov(unsigned Opcode) const; 46 47 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const; 48 49 virtual int getIndirectIndexBegin(const MachineFunction &MF) const; 50 51 virtual int getIndirectIndexEnd(const MachineFunction &MF) const; 52 53 virtual unsigned calculateIndirectAddress(unsigned RegIndex, 54 unsigned Channel) const; 55 56 virtual const TargetRegisterClass *getIndirectAddrStoreRegClass( 57 unsigned SourceReg) const; 58 59 virtual const TargetRegisterClass *getIndirectAddrLoadRegClass() const; 60 61 virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB, 62 MachineBasicBlock::iterator I, 63 unsigned ValueReg, 64 unsigned Address, 65 unsigned OffsetReg) const; 66 67 virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB, 68 MachineBasicBlock::iterator I, 69 unsigned ValueReg, 70 unsigned Address, 71 unsigned OffsetReg) const; 72 73 virtual const TargetRegisterClass *getSuperIndirectRegClass() const; 74 }; 75 76 namespace AMDGPU { 77 78 int getVOPe64(uint16_t Opcode); 79 80 } // End namespace AMDGPU 81 82 } // End namespace llvm 83 84 namespace SIInstrFlags { 85 enum Flags { 86 // First 4 bits are the instruction encoding 87 VM_CNT = 1 << 0, 88 EXP_CNT = 1 << 1, 89 LGKM_CNT = 1 << 2 90 }; 91 } 92 93 #endif //SIINSTRINFO_H 94
