/external/llvm/lib/Target/Mips/ |
Mips16RegisterInfo.cpp | 99 unsigned FrameReg; 102 FrameReg = Mips::SP; 106 FrameReg = Mips::S0; 110 FrameReg = MI.getOperand(OpNo+2).getReg(); 112 FrameReg = Mips::SP; 132 if (!MI.isDebugValue() && ( ((FrameReg != Mips::SP) && !isInt<16>(Offset)) || 133 ((FrameReg == Mips::SP) && !isInt<15>(Offset)) )) { 137 FrameReg = TII.loadImmediate(FrameReg, Offset, MBB, II, DL, NewImm); 141 MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill) [all...] |
MipsSERegisterInfo.cpp | 84 unsigned FrameReg; 87 FrameReg = Subtarget.isABI_N64() ? Mips::SP_64 : Mips::SP; 89 FrameReg = getFrameRegister(MF); 115 BuildMI(MBB, II, DL, TII.get(ADDu), Reg).addReg(FrameReg) 118 FrameReg = Reg; 123 MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill);
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/external/llvm/lib/Target/AArch64/ |
AArch64RegisterInfo.cpp | 110 unsigned FrameReg; 112 Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj, 120 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, /*isDef=*/ false); 142 BaseReg, FrameReg, BaseReg, Offset); 143 FrameReg = BaseReg; 151 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, true);
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/external/llvm/lib/Target/Hexagon/ |
HexagonRegisterInfo.cpp | 135 unsigned FrameReg = getFrameRegister(MF); 180 dstReg).addReg(FrameReg).addReg(dstReg); 184 dstReg).addReg(FrameReg).addImm(Offset); 209 resReg).addReg(FrameReg).addReg(resReg); 213 resReg).addReg(FrameReg).addImm(Offset); 229 resReg).addReg(FrameReg).addReg(resReg); 236 resReg).addReg(FrameReg).addImm(Offset); 247 dstReg).addReg(FrameReg).addReg(dstReg); 255 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false);
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/external/llvm/lib/Target/XCore/ |
XCoreRegisterInfo.cpp | 131 unsigned FrameReg = getFrameRegister(MF); 135 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/); 172 .addReg(FrameReg) 178 .addReg(FrameReg) 183 .addReg(FrameReg) 193 .addReg(FrameReg) 199 .addReg(FrameReg) 204 .addReg(FrameReg)
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/external/llvm/lib/Target/ARM/ |
ARMBaseRegisterInfo.cpp | 674 unsigned FrameReg; 676 int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj); 683 if (RS && FrameReg == ARM::SP && FrameIndex == RS->getScavengingFrameIndex()){ 695 MI.getOperand(FIOperandNum). ChangeToRegister(FrameReg, false /*isDef*/); 703 Done = rewriteARMFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII); 706 Done = rewriteT2FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII); 726 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, false); 730 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 734 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
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ARMFrameLowering.cpp | 484 unsigned &FrameReg) const { 485 return ResolveFrameIndexReference(MF, FI, FrameReg, 0); 490 int FI, unsigned &FrameReg, 500 FrameReg = ARM::SP; 518 FrameReg = RegInfo->getFrameRegister(MF); 523 FrameReg = RegInfo->getBaseRegister(); 533 FrameReg = RegInfo->getFrameRegister(MF); 542 FrameReg = RegInfo->getFrameRegister(MF); 555 FrameReg = RegInfo->getFrameRegister(MF); 560 FrameReg = RegInfo->getFrameRegister(MF) [all...] |
ARMISelLowering.cpp | [all...] |
/external/llvm/lib/CodeGen/AsmPrinter/ |
DwarfCompileUnit.cpp | [all...] |
/external/llvm/lib/Target/Sparc/ |
SparcISelLowering.cpp | [all...] |
/external/llvm/lib/Target/PowerPC/ |
PPCISelLowering.cpp | [all...] |
/external/llvm/lib/Target/X86/ |
X86ISelLowering.cpp | [all...] |