1 //===---- LiveRangeEdit.h - Basic tools for split and spill -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // The LiveRangeEdit class represents changes done to a virtual register when it 11 // is spilled or split. 12 // 13 // The parent register is never changed. Instead, a number of new virtual 14 // registers are created and added to the newRegs vector. 15 // 16 //===----------------------------------------------------------------------===// 17 18 #ifndef LLVM_CODEGEN_LIVERANGEEDIT_H 19 #define LLVM_CODEGEN_LIVERANGEEDIT_H 20 21 #include "llvm/ADT/ArrayRef.h" 22 #include "llvm/ADT/SmallPtrSet.h" 23 #include "llvm/CodeGen/LiveInterval.h" 24 #include "llvm/Target/TargetMachine.h" 25 26 namespace llvm { 27 28 class AliasAnalysis; 29 class LiveIntervals; 30 class MachineLoopInfo; 31 class MachineRegisterInfo; 32 class VirtRegMap; 33 34 class LiveRangeEdit { 35 public: 36 /// Callback methods for LiveRangeEdit owners. 37 class Delegate { 38 virtual void anchor(); 39 public: 40 /// Called immediately before erasing a dead machine instruction. 41 virtual void LRE_WillEraseInstruction(MachineInstr *MI) {} 42 43 /// Called when a virtual register is no longer used. Return false to defer 44 /// its deletion from LiveIntervals. 45 virtual bool LRE_CanEraseVirtReg(unsigned) { return true; } 46 47 /// Called before shrinking the live range of a virtual register. 48 virtual void LRE_WillShrinkVirtReg(unsigned) {} 49 50 /// Called after cloning a virtual register. 51 /// This is used for new registers representing connected components of Old. 52 virtual void LRE_DidCloneVirtReg(unsigned New, unsigned Old) {} 53 54 virtual ~Delegate() {} 55 }; 56 57 private: 58 LiveInterval *Parent; 59 SmallVectorImpl<LiveInterval*> &NewRegs; 60 MachineRegisterInfo &MRI; 61 LiveIntervals &LIS; 62 VirtRegMap *VRM; 63 const TargetInstrInfo &TII; 64 Delegate *const TheDelegate; 65 66 /// FirstNew - Index of the first register added to NewRegs. 67 const unsigned FirstNew; 68 69 /// ScannedRemattable - true when remattable values have been identified. 70 bool ScannedRemattable; 71 72 /// Remattable - Values defined by remattable instructions as identified by 73 /// tii.isTriviallyReMaterializable(). 74 SmallPtrSet<const VNInfo*,4> Remattable; 75 76 /// Rematted - Values that were actually rematted, and so need to have their 77 /// live range trimmed or entirely removed. 78 SmallPtrSet<const VNInfo*,4> Rematted; 79 80 /// scanRemattable - Identify the Parent values that may rematerialize. 81 void scanRemattable(AliasAnalysis *aa); 82 83 /// allUsesAvailableAt - Return true if all registers used by OrigMI at 84 /// OrigIdx are also available with the same value at UseIdx. 85 bool allUsesAvailableAt(const MachineInstr *OrigMI, SlotIndex OrigIdx, 86 SlotIndex UseIdx); 87 88 /// foldAsLoad - If LI has a single use and a single def that can be folded as 89 /// a load, eliminate the register by folding the def into the use. 90 bool foldAsLoad(LiveInterval *LI, SmallVectorImpl<MachineInstr*> &Dead); 91 92 public: 93 /// Create a LiveRangeEdit for breaking down parent into smaller pieces. 94 /// @param parent The register being spilled or split. 95 /// @param newRegs List to receive any new registers created. This needn't be 96 /// empty initially, any existing registers are ignored. 97 /// @param MF The MachineFunction the live range edit is taking place in. 98 /// @param lis The collection of all live intervals in this function. 99 /// @param vrm Map of virtual registers to physical registers for this 100 /// function. If NULL, no virtual register map updates will 101 /// be done. This could be the case if called before Regalloc. 102 LiveRangeEdit(LiveInterval *parent, 103 SmallVectorImpl<LiveInterval*> &newRegs, 104 MachineFunction &MF, 105 LiveIntervals &lis, 106 VirtRegMap *vrm, 107 Delegate *delegate = 0) 108 : Parent(parent), NewRegs(newRegs), 109 MRI(MF.getRegInfo()), LIS(lis), VRM(vrm), 110 TII(*MF.getTarget().getInstrInfo()), 111 TheDelegate(delegate), 112 FirstNew(newRegs.size()), 113 ScannedRemattable(false) {} 114 115 LiveInterval &getParent() const { 116 assert(Parent && "No parent LiveInterval"); 117 return *Parent; 118 } 119 unsigned getReg() const { return getParent().reg; } 120 121 /// Iterator for accessing the new registers added by this edit. 122 typedef SmallVectorImpl<LiveInterval*>::const_iterator iterator; 123 iterator begin() const { return NewRegs.begin()+FirstNew; } 124 iterator end() const { return NewRegs.end(); } 125 unsigned size() const { return NewRegs.size()-FirstNew; } 126 bool empty() const { return size() == 0; } 127 LiveInterval *get(unsigned idx) const { return NewRegs[idx+FirstNew]; } 128 129 ArrayRef<LiveInterval*> regs() const { 130 return makeArrayRef(NewRegs).slice(FirstNew); 131 } 132 133 /// createFrom - Create a new virtual register based on OldReg. 134 LiveInterval &createFrom(unsigned OldReg); 135 136 /// create - Create a new register with the same class and original slot as 137 /// parent. 138 LiveInterval &create() { 139 return createFrom(getReg()); 140 } 141 142 /// anyRematerializable - Return true if any parent values may be 143 /// rematerializable. 144 /// This function must be called before any rematerialization is attempted. 145 bool anyRematerializable(AliasAnalysis*); 146 147 /// checkRematerializable - Manually add VNI to the list of rematerializable 148 /// values if DefMI may be rematerializable. 149 bool checkRematerializable(VNInfo *VNI, const MachineInstr *DefMI, 150 AliasAnalysis*); 151 152 /// Remat - Information needed to rematerialize at a specific location. 153 struct Remat { 154 VNInfo *ParentVNI; // parent_'s value at the remat location. 155 MachineInstr *OrigMI; // Instruction defining ParentVNI. 156 explicit Remat(VNInfo *ParentVNI) : ParentVNI(ParentVNI), OrigMI(0) {} 157 }; 158 159 /// canRematerializeAt - Determine if ParentVNI can be rematerialized at 160 /// UseIdx. It is assumed that parent_.getVNINfoAt(UseIdx) == ParentVNI. 161 /// When cheapAsAMove is set, only cheap remats are allowed. 162 bool canRematerializeAt(Remat &RM, 163 SlotIndex UseIdx, 164 bool cheapAsAMove); 165 166 /// rematerializeAt - Rematerialize RM.ParentVNI into DestReg by inserting an 167 /// instruction into MBB before MI. The new instruction is mapped, but 168 /// liveness is not updated. 169 /// Return the SlotIndex of the new instruction. 170 SlotIndex rematerializeAt(MachineBasicBlock &MBB, 171 MachineBasicBlock::iterator MI, 172 unsigned DestReg, 173 const Remat &RM, 174 const TargetRegisterInfo&, 175 bool Late = false); 176 177 /// markRematerialized - explicitly mark a value as rematerialized after doing 178 /// it manually. 179 void markRematerialized(const VNInfo *ParentVNI) { 180 Rematted.insert(ParentVNI); 181 } 182 183 /// didRematerialize - Return true if ParentVNI was rematerialized anywhere. 184 bool didRematerialize(const VNInfo *ParentVNI) const { 185 return Rematted.count(ParentVNI); 186 } 187 188 /// eraseVirtReg - Notify the delegate that Reg is no longer in use, and try 189 /// to erase it from LIS. 190 void eraseVirtReg(unsigned Reg); 191 192 /// eliminateDeadDefs - Try to delete machine instructions that are now dead 193 /// (allDefsAreDead returns true). This may cause live intervals to be trimmed 194 /// and further dead efs to be eliminated. 195 /// RegsBeingSpilled lists registers currently being spilled by the register 196 /// allocator. These registers should not be split into new intervals 197 /// as currently those new intervals are not guaranteed to spill. 198 void eliminateDeadDefs(SmallVectorImpl<MachineInstr*> &Dead, 199 ArrayRef<unsigned> RegsBeingSpilled 200 = ArrayRef<unsigned>()); 201 202 /// calculateRegClassAndHint - Recompute register class and hint for each new 203 /// register. 204 void calculateRegClassAndHint(MachineFunction&, 205 const MachineLoopInfo&); 206 }; 207 208 } 209 210 #endif 211
