| /external/llvm/lib/CodeGen/ |
| CallingConvLower.cpp | 120 unsigned NumOps = Outs.size();
121 for (unsigned i = 0; i != NumOps; ++i) {
139 unsigned NumOps = ArgVTs.size();
140 for (unsigned i = 0; i != NumOps; ++i) {
|
| MachineInstr.cpp | 538 if (unsigned NumOps = MCID->getNumOperands() +
540 CapOperands = OperandCapacity::get(NumOps);
601 /// Move NumOps MachineOperands from Src to Dst, with support for overlapping
604 unsigned NumOps, MachineRegisterInfo *MRI) {
606 return MRI->moveOperands(Dst, Src, NumOps);
611 for (unsigned i = 0; i != NumOps; ++i)
614 for (unsigned i = NumOps; i ; --i)
[all...] |
| MachineVerifier.cpp | 735 unsigned NumOps;
736 for (unsigned e = MI->getNumOperands(); OpNo < e; OpNo += NumOps) {
741 NumOps = 1 + InlineAsm::getNumOperandRegisters(MO.getImm());
[all...] |
| TwoAddressInstructionPass.cpp | 430 unsigned NumOps = MI.isInlineAsm()
432 for (unsigned i = 0; i != NumOps; ++i) {
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonCallingConvLower.cpp | 136 unsigned NumOps = Outs.size();
146 for (; i != NumOps; ++i) {
164 unsigned NumOps = ArgVTs.size();
165 for (unsigned i = 0; i != NumOps; ++i) {
|
| HexagonISelLowering.cpp | 681 unsigned NumOps = Node->getNumOperands();
682 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
683 --NumOps; // Ignore the flag operand.
685 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86CodeEmitter.cpp | 177 unsigned NumOps = Desc.getNumOperands();
178 if (NumOps) {
179 bool isTwoAddr = NumOps > 1 &&
184 for (unsigned e = NumOps; i != e; ++i) {
202 for (unsigned e = NumOps; i != e; ++i) {
214 for (; i != NumOps; ++i) {
231 if (NumOps > e && X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(e)))
248 for (unsigned e = NumOps; i != e; ++i) {
[all...] |
| X86ISelDAGToDAG.cpp | 387 unsigned NumOps = Call.getNode()->getNumOperands();
390 for (unsigned i = 1, e = NumOps; i != e; ++i)
392 CurDAG->UpdateNodeOperands(Call.getNode(), &Ops[0], NumOps);
[all...] |
| X86InstrInfo.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGSDNodes.cpp | 209 unsigned NumOps = Node->getNumOperands();
210 if (Node->getOperand(NumOps-1).getValueType() == MVT::Other)
211 Chain = Node->getOperand(NumOps-1).getNode();
[all...] |
| LegalizeTypes.cpp | 415 for (unsigned i = 0, NumOps = I->getNumOperands(); i < NumOps; ++i)
[all...] |
| ScheduleDAGFast.cpp | 487 unsigned NumOps = Node->getNumOperands();
488 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
489 --NumOps; // Ignore the glue operand.
491 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
674 unsigned NumOps = N->getNumOperands();
675 if (unsigned NumLeft = NumOps) {
681 if (NumLeft == NumOps && Op.getValueType() == MVT::Glue) {
|
| ScheduleDAGRRList.cpp | [all...] |
| LegalizeVectorTypes.cpp | [all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenInstruction.cpp | 71 unsigned NumOps = 1;
91 NumOps = NumArgs;
116 OperandType, MIOperandNo, NumOps,
118 MIOperandNo += NumOps;
|
| DAGISelMatcherEmitter.cpp | 647 unsigned NumOps = P.getNumOperands();
650 ++NumOps; // Get the chained node too.
653 OS << " Result.resize(NextRes+" << NumOps << ");\n";
668 for (unsigned i = 0; i != NumOps; ++i)
|
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.cpp | 557 unsigned NumOps = Desc->getNumOperands();
564 assert(!DescE64 || DescE64->getNumOperands() == (NumOps + 4));
571 i != e && Op < NumOps; ++i, ++Op) {
599 i != e && Op < NumOps; ++i, ++Op) {
656 for (unsigned i = NumOps - NumDefs, e = Node->getNumOperands(); i < e; ++i)
|
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCCodeEmitter.cpp | 566 unsigned NumOps = Desc.getNumOperands();
568 if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) == 0)
570 else if (NumOps > 3 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0) {
571 assert(Desc.getOperandConstraint(NumOps - 1, MCOI::TIED_TO) == 1);
741 unsigned NumOps = MI.getNumOperands();
743 bool isTwoAddr = NumOps > 1 &&
748 for (; i != NumOps; ++i) {
766 for (; i != NumOps; ++i) {
778 for (; i != NumOps; ++i) {
795 if (NumOps > e && MI.getOperand(e).isReg() &
[all...] |
| /external/llvm/lib/Linker/ |
| LinkModules.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb2SizeReduction.cpp | 675 unsigned NumOps = MCID.getNumOperands();
676 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR);
677 if (HasCC && MI->getOperand(NumOps-1).isDead())
701 unsigned NumOps = MCID.getNumOperands();
703 if (i < NumOps && MCID.OpInfo[i].isOptionalDef())
772 unsigned NumOps = MCID.getNumOperands();
773 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR);
774 if (HasCC && MI->getOperand(NumOps-1).isDead())
798 unsigned NumOps = MCID.getNumOperands();
800 if (i < NumOps && MCID.OpInfo[i].isOptionalDef()
[all...] |
| ARMConstantIslandPass.cpp | [all...] |
| ARMISelDAGToDAG.cpp | [all...] |
| ARMBaseInstrInfo.cpp | 153 unsigned NumOps = MCID.getNumOperands();
157 const MachineOperand &Offset = MI->getOperand(NumOps-3);
161 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
162 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
611 unsigned NumOps = MCID.getNumOperands();
613 MI->getOperand(NumOps - (MI->isPredicable() ? 3 : 2));
[all...] |
| /external/llvm/lib/IR/ |
| Instructions.cpp | 144 unsigned NumOps = e + e / 2;
145 if (NumOps < 2) NumOps = 2; // 2 op PHI nodes are VERY common.
150 ReservedSpace = NumOps;
[all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | 622 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
624 for (unsigned i = 0; i < NumOps; ++i, ++I) {
687 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
689 for (unsigned i = 0; i < NumOps; ++i, ++I) {
[all...] |
