| /external/llvm/lib/Target/ARM/ |
| Thumb2InstrInfo.cpp | 60 unsigned PredReg = 0;
61 ARMCC::CondCodes CC = getInstrPredicate(Tail, PredReg);
108 unsigned PredReg = 0;
109 return getITInstrPredicate(MBBI, PredReg) == ARMCC::AL;
180 ARMCC::CondCodes Pred, unsigned PredReg,
195 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
202 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
211 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
217 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
403 unsigned PredReg;
[all...] |
| MLxExpansionPass.cpp | 284 unsigned PredReg = MI->getOperand(++NextOp).getReg();
297 MIB.addImm(Pred).addReg(PredReg);
309 MIB.addImm(Pred).addReg(PredReg);
|
| Thumb2ITBlockPass.cpp | 169 unsigned PredReg = 0;
170 ARMCC::CondCodes CC = getITInstrPredicate(MI, PredReg);
|
| ARMBaseRegisterInfo.cpp | 370 unsigned PredReg, unsigned MIFlags) const {
380 .addImm(0).addImm(Pred).addReg(PredReg)
723 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
731 Offset, Pred, PredReg, TII);
735 Offset, Pred, PredReg, TII);
|
| ARMExpandPseudoInsts.cpp | 615 unsigned PredReg = 0;
616 ARMCC::CondCodes Pred = getInstrPredicate(&MI, PredReg);
[all...] |
| ARMFrameLowering.cpp | 123 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
126 Pred, PredReg, TII, MIFlags);
129 Pred, PredReg, TII, MIFlags);
[all...] |
| Thumb2SizeReduction.cpp | 555 unsigned PredReg = 0;
556 if (getInstrPredicate(MI, PredReg) == ARMCC::AL) {
660 unsigned PredReg = 0;
661 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
758 unsigned PredReg = 0;
759 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
[all...] |
| ARMConstantIslandPass.cpp | [all...] |
| ARMISelDAGToDAG.cpp | [all...] |
| ARMLoadStoreOptimizer.cpp | 95 ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch,
109 unsigned PredReg,
115 ARMCC::CondCodes Pred, unsigned PredReg,
286 unsigned PredReg, unsigned Scratch, DebugLoc dl,
340 .addImm(Pred).addReg(PredReg).addReg(0);
351 .addImm(Pred).addReg(PredReg);
371 ARMCC::CondCodes Pred, unsigned PredReg,
416 Pred, PredReg, Scratch, dl, Regs, ImpDefs))
448 ARMCC::CondCodes Pred, unsigned PredReg,
499 Base, false, Opcode, Pred, PredReg, Scratch, dl, Merges)
[all...] |
| ARMBaseInstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCCTRLoops.cpp | 326 unsigned PredReg = LastI->getOperand(1).getReg();
370 MI->getOperand(0).getReg() == PredReg) {
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonHardwareLoops.cpp | 500 unsigned PredReg = Cond[Cond.size()-1].getReg();
501 MachineInstr *CondI = MRI->getVRegDef(PredReg);
[all...] |
