1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that Mips uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef MipsISELLOWERING_H 16 #define MipsISELLOWERING_H 17 18 #include "Mips.h" 19 #include "MipsSubtarget.h" 20 #include "llvm/CodeGen/CallingConvLower.h" 21 #include "llvm/CodeGen/SelectionDAG.h" 22 #include "llvm/IR/Function.h" 23 #include "llvm/Target/TargetLowering.h" 24 #include <deque> 25 #include <string> 26 27 namespace llvm { 28 namespace MipsISD { 29 enum NodeType { 30 // Start the numbering from where ISD NodeType finishes. 31 FIRST_NUMBER = ISD::BUILTIN_OP_END, 32 33 // Jump and link (call) 34 JmpLink, 35 36 // Tail call 37 TailCall, 38 39 // Get the Higher 16 bits from a 32-bit immediate 40 // No relation with Mips Hi register 41 Hi, 42 43 // Get the Lower 16 bits from a 32-bit immediate 44 // No relation with Mips Lo register 45 Lo, 46 47 // Handle gp_rel (small data/bss sections) relocation. 48 GPRel, 49 50 // Thread Pointer 51 ThreadPointer, 52 53 // Floating Point Branch Conditional 54 FPBrcond, 55 56 // Floating Point Compare 57 FPCmp, 58 59 // Floating Point Conditional Moves 60 CMovFP_T, 61 CMovFP_F, 62 63 // Floating Point Rounding 64 FPRound, 65 66 // Return 67 Ret, 68 69 EH_RETURN, 70 71 // MAdd/Sub nodes 72 MAdd, 73 MAddu, 74 MSub, 75 MSubu, 76 77 // DivRem(u) 78 DivRem, 79 DivRemU, 80 81 BuildPairF64, 82 ExtractElementF64, 83 84 Wrapper, 85 86 DynAlloc, 87 88 Sync, 89 90 Ext, 91 Ins, 92 93 // EXTR.W instrinsic nodes. 94 EXTP, 95 EXTPDP, 96 EXTR_S_H, 97 EXTR_W, 98 EXTR_R_W, 99 EXTR_RS_W, 100 SHILO, 101 MTHLIP, 102 103 // DPA.W intrinsic nodes. 104 MULSAQ_S_W_PH, 105 MAQ_S_W_PHL, 106 MAQ_S_W_PHR, 107 MAQ_SA_W_PHL, 108 MAQ_SA_W_PHR, 109 DPAU_H_QBL, 110 DPAU_H_QBR, 111 DPSU_H_QBL, 112 DPSU_H_QBR, 113 DPAQ_S_W_PH, 114 DPSQ_S_W_PH, 115 DPAQ_SA_L_W, 116 DPSQ_SA_L_W, 117 DPA_W_PH, 118 DPS_W_PH, 119 DPAQX_S_W_PH, 120 DPAQX_SA_W_PH, 121 DPAX_W_PH, 122 DPSX_W_PH, 123 DPSQX_S_W_PH, 124 DPSQX_SA_W_PH, 125 MULSA_W_PH, 126 127 MULT, 128 MULTU, 129 MADD_DSP, 130 MADDU_DSP, 131 MSUB_DSP, 132 MSUBU_DSP, 133 134 // Load/Store Left/Right nodes. 135 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE, 136 LWR, 137 SWL, 138 SWR, 139 LDL, 140 LDR, 141 SDL, 142 SDR 143 }; 144 } 145 146 //===--------------------------------------------------------------------===// 147 // TargetLowering Implementation 148 //===--------------------------------------------------------------------===// 149 class MipsFunctionInfo; 150 151 class MipsTargetLowering : public TargetLowering { 152 public: 153 explicit MipsTargetLowering(MipsTargetMachine &TM); 154 155 static const MipsTargetLowering *create(MipsTargetMachine &TM); 156 157 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; } 158 159 virtual void LowerOperationWrapper(SDNode *N, 160 SmallVectorImpl<SDValue> &Results, 161 SelectionDAG &DAG) const; 162 163 /// LowerOperation - Provide custom lowering hooks for some operations. 164 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 165 166 /// ReplaceNodeResults - Replace the results of node with an illegal result 167 /// type with new values built out of custom code. 168 /// 169 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 170 SelectionDAG &DAG) const; 171 172 /// getTargetNodeName - This method returns the name of a target specific 173 // DAG node. 174 virtual const char *getTargetNodeName(unsigned Opcode) const; 175 176 /// getSetCCResultType - get the ISD::SETCC result ValueType 177 EVT getSetCCResultType(EVT VT) const; 178 179 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 180 181 virtual MachineBasicBlock * 182 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const; 183 184 struct LTStr { 185 bool operator()(const char *S1, const char *S2) const { 186 return strcmp(S1, S2) < 0; 187 } 188 }; 189 190 protected: 191 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const; 192 193 SDValue getAddrLocal(SDValue Op, SelectionDAG &DAG, bool HasMips64) const; 194 195 SDValue getAddrGlobal(SDValue Op, SelectionDAG &DAG, unsigned Flag) const; 196 197 SDValue getAddrGlobalLargeGOT(SDValue Op, SelectionDAG &DAG, 198 unsigned HiFlag, unsigned LoFlag) const; 199 200 /// This function fills Ops, which is the list of operands that will later 201 /// be used when a function call node is created. It also generates 202 /// copyToReg nodes to set up argument registers. 203 virtual void 204 getOpndList(SmallVectorImpl<SDValue> &Ops, 205 std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 206 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 207 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const; 208 209 /// ByValArgInfo - Byval argument information. 210 struct ByValArgInfo { 211 unsigned FirstIdx; // Index of the first register used. 212 unsigned NumRegs; // Number of registers used for this argument. 213 unsigned Address; // Offset of the stack area used to pass this argument. 214 215 ByValArgInfo() : FirstIdx(0), NumRegs(0), Address(0) {} 216 }; 217 218 /// MipsCC - This class provides methods used to analyze formal and call 219 /// arguments and inquire about calling convention information. 220 class MipsCC { 221 public: 222 MipsCC(CallingConv::ID CallConv, bool IsO32, CCState &Info); 223 224 void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, 225 bool IsVarArg, bool IsSoftFloat, 226 const SDNode *CallNode, 227 std::vector<ArgListEntry> &FuncArgs); 228 void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins, 229 bool IsSoftFloat, 230 Function::const_arg_iterator FuncArg); 231 232 void analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, 233 bool IsSoftFloat, const SDNode *CallNode, 234 const Type *RetTy) const; 235 236 void analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, 237 bool IsSoftFloat, const Type *RetTy) const; 238 239 const CCState &getCCInfo() const { return CCInfo; } 240 241 /// hasByValArg - Returns true if function has byval arguments. 242 bool hasByValArg() const { return !ByValArgs.empty(); } 243 244 /// regSize - Size (in number of bits) of integer registers. 245 unsigned regSize() const { return IsO32 ? 4 : 8; } 246 247 /// numIntArgRegs - Number of integer registers available for calls. 248 unsigned numIntArgRegs() const; 249 250 /// reservedArgArea - The size of the area the caller reserves for 251 /// register arguments. This is 16-byte if ABI is O32. 252 unsigned reservedArgArea() const; 253 254 /// Return pointer to array of integer argument registers. 255 const uint16_t *intArgRegs() const; 256 257 typedef SmallVector<ByValArgInfo, 2>::const_iterator byval_iterator; 258 byval_iterator byval_begin() const { return ByValArgs.begin(); } 259 byval_iterator byval_end() const { return ByValArgs.end(); } 260 261 private: 262 void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT, 263 CCValAssign::LocInfo LocInfo, 264 ISD::ArgFlagsTy ArgFlags); 265 266 /// useRegsForByval - Returns true if the calling convention allows the 267 /// use of registers to pass byval arguments. 268 bool useRegsForByval() const { return CallConv != CallingConv::Fast; } 269 270 /// Return the function that analyzes fixed argument list functions. 271 llvm::CCAssignFn *fixedArgFn() const; 272 273 /// Return the function that analyzes variable argument list functions. 274 llvm::CCAssignFn *varArgFn() const; 275 276 const uint16_t *shadowRegs() const; 277 278 void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize, 279 unsigned Align); 280 281 /// Return the type of the register which is used to pass an argument or 282 /// return a value. This function returns f64 if the argument is an i64 283 /// value which has been generated as a result of softening an f128 value. 284 /// Otherwise, it just returns VT. 285 MVT getRegVT(MVT VT, const Type *OrigTy, const SDNode *CallNode, 286 bool IsSoftFloat) const; 287 288 template<typename Ty> 289 void analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat, 290 const SDNode *CallNode, const Type *RetTy) const; 291 292 CCState &CCInfo; 293 CallingConv::ID CallConv; 294 bool IsO32; 295 SmallVector<ByValArgInfo, 2> ByValArgs; 296 }; 297 298 // Subtarget Info 299 const MipsSubtarget *Subtarget; 300 301 bool HasMips64, IsN64, IsO32; 302 303 private: 304 // Lower Operand helpers 305 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 306 CallingConv::ID CallConv, bool isVarArg, 307 const SmallVectorImpl<ISD::InputArg> &Ins, 308 DebugLoc dl, SelectionDAG &DAG, 309 SmallVectorImpl<SDValue> &InVals, 310 const SDNode *CallNode, const Type *RetTy) const; 311 312 // Lower Operand specifics 313 SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const; 314 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 315 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 316 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 317 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 318 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 319 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 320 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const; 321 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 322 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const; 323 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const; 324 SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; 325 SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const; 326 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 327 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 328 SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const; 329 SDValue lowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const; 330 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const; 331 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const; 332 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG, 333 bool IsSRA) const; 334 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const; 335 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const; 336 SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 337 SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; 338 SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const; 339 340 /// isEligibleForTailCallOptimization - Check whether the call is eligible 341 /// for tail call optimization. 342 virtual bool 343 isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo, 344 unsigned NextStackOffset, 345 const MipsFunctionInfo& FI) const = 0; 346 347 /// copyByValArg - Copy argument registers which were used to pass a byval 348 /// argument to the stack. Create a stack frame object for the byval 349 /// argument. 350 void copyByValRegs(SDValue Chain, DebugLoc DL, 351 std::vector<SDValue> &OutChains, SelectionDAG &DAG, 352 const ISD::ArgFlagsTy &Flags, 353 SmallVectorImpl<SDValue> &InVals, 354 const Argument *FuncArg, 355 const MipsCC &CC, const ByValArgInfo &ByVal) const; 356 357 /// passByValArg - Pass a byval argument in registers or on stack. 358 void passByValArg(SDValue Chain, DebugLoc DL, 359 std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 360 SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr, 361 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, 362 const MipsCC &CC, const ByValArgInfo &ByVal, 363 const ISD::ArgFlagsTy &Flags, bool isLittle) const; 364 365 /// writeVarArgRegs - Write variable function arguments passed in registers 366 /// to the stack. Also create a stack frame object for the first variable 367 /// argument. 368 void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC, 369 SDValue Chain, DebugLoc DL, SelectionDAG &DAG) const; 370 371 virtual SDValue 372 LowerFormalArguments(SDValue Chain, 373 CallingConv::ID CallConv, bool isVarArg, 374 const SmallVectorImpl<ISD::InputArg> &Ins, 375 DebugLoc dl, SelectionDAG &DAG, 376 SmallVectorImpl<SDValue> &InVals) const; 377 378 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain, 379 SDValue Arg, DebugLoc DL, bool IsTailCall, 380 SelectionDAG &DAG) const; 381 382 virtual SDValue 383 LowerCall(TargetLowering::CallLoweringInfo &CLI, 384 SmallVectorImpl<SDValue> &InVals) const; 385 386 virtual bool 387 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 388 bool isVarArg, 389 const SmallVectorImpl<ISD::OutputArg> &Outs, 390 LLVMContext &Context) const; 391 392 virtual SDValue 393 LowerReturn(SDValue Chain, 394 CallingConv::ID CallConv, bool isVarArg, 395 const SmallVectorImpl<ISD::OutputArg> &Outs, 396 const SmallVectorImpl<SDValue> &OutVals, 397 DebugLoc dl, SelectionDAG &DAG) const; 398 399 // Inline asm support 400 ConstraintType getConstraintType(const std::string &Constraint) const; 401 402 /// Examine constraint string and operand type and determine a weight value. 403 /// The operand object must already have been set up with the operand type. 404 ConstraintWeight getSingleConstraintMatchWeight( 405 AsmOperandInfo &info, const char *constraint) const; 406 407 std::pair<unsigned, const TargetRegisterClass*> 408 getRegForInlineAsmConstraint(const std::string &Constraint, 409 EVT VT) const; 410 411 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 412 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 413 /// true it means one of the asm constraint of the inline asm instruction 414 /// being processed is 'm'. 415 virtual void LowerAsmOperandForConstraint(SDValue Op, 416 std::string &Constraint, 417 std::vector<SDValue> &Ops, 418 SelectionDAG &DAG) const; 419 420 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const; 421 422 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 423 424 virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 425 unsigned SrcAlign, 426 bool IsMemset, bool ZeroMemset, 427 bool MemcpyStrSrc, 428 MachineFunction &MF) const; 429 430 /// isFPImmLegal - Returns true if the target can instruction select the 431 /// specified FP immediate natively. If false, the legalizer will 432 /// materialize the FP immediate as a load from a constant pool. 433 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const; 434 435 virtual unsigned getJumpTableEncoding() const; 436 437 MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 438 unsigned Size, unsigned BinOpcode, bool Nand = false) const; 439 MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI, 440 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode, 441 bool Nand = false) const; 442 MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI, 443 MachineBasicBlock *BB, unsigned Size) const; 444 MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI, 445 MachineBasicBlock *BB, unsigned Size) const; 446 }; 447 448 /// Create MipsTargetLowering objects. 449 const MipsTargetLowering *createMips16TargetLowering(MipsTargetMachine &TM); 450 const MipsTargetLowering *createMipsSETargetLowering(MipsTargetMachine &TM); 451 } 452 453 #endif // MipsISELLOWERING_H 454
