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    Searched defs:SchedModel (Results 1 - 9 of 9) sorted by null

  /external/llvm/lib/MC/
MCSubtargetInfo.cpp 104 assert(Found->Value && "Missing processor SchedModel value");
110 const MCSchedModel *SchedModel = getSchedModelForCPU(CPU);
111 return InstrItineraryData(SchedModel, Stages, OperandCycles, ForwardingPaths);
  /external/llvm/include/llvm/CodeGen/
TargetSchedule.h 35 MCSchedModel SchedModel;
67 const MCSchedModel *getMCSchedModel() const { return &SchedModel; }
82 unsigned getProcessorID() const { return SchedModel.getProcessorID(); }
85 unsigned getIssueWidth() const { return SchedModel.IssueWidth; }
88 unsigned getILPWindow() const { return SchedModel.ILPWindow; }
96 return SchedModel.getNumProcResourceKinds();
101 return SchedModel.getProcResource(PIdx);
MachineTraceMetrics.h 73 TargetSchedModel SchedModel;
ScheduleDAGInstrs.h 79 TargetSchedModel SchedModel;
150 const TargetSchedModel *getSchedModel() const { return &SchedModel; }
155 SU->SchedClass = SchedModel.resolveSchedClass(SU->getInstr());
  /external/llvm/include/llvm/MC/
MCInstrItineraries.h 113 const MCSchedModel *SchedModel; ///< Basic machine properties.
121 InstrItineraryData() : SchedModel(&MCSchedModel::DefaultSchedModel),
127 : SchedModel(SM), Stages(S), OperandCycles(OS), Forwardings(F),
128 Itineraries(SchedModel->InstrItineraries) {}
170 return SchedModel->MinLatency < 0 ? 1 : SchedModel->MinLatency;
  /external/llvm/lib/Target/Hexagon/
HexagonMachineScheduler.h 48 const TargetSchedModel *SchedModel;
59 SchedModel(SM), TotalPackets(0) {
66 Packet.resize(SchedModel->getIssueWidth());
135 const TargetSchedModel *SchedModel;
156 DAG(0), SchedModel(0), Available(ID, Name+".A"),
169 SchedModel = smodel;
192 const TargetSchedModel *SchedModel;
208 DAG(0), SchedModel(0), TRI(0), Top(TopQID, "TopQ"), Bot(BotQID, "BotQ") {}
  /external/llvm/lib/CodeGen/
EarlyIfConversion.cpp 582 const MCSchedModel *SchedModel;
690 unsigned CritLimit = SchedModel->MispredictPenalty/2;
780 SchedModel =
MachineScheduler.cpp     [all...]
  /external/llvm/lib/Target/ARM/
ARMSubtarget.h 172 /// SchedModel - Processor specific instruction costs.
173 const MCSchedModel *SchedModel;

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