1 //===- FastISelEmitter.cpp - Generate an instruction selector -------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This tablegen backend emits code for use by the "fast" instruction 11 // selection algorithm. See the comments at the top of 12 // lib/CodeGen/SelectionDAG/FastISel.cpp for background. 13 // 14 // This file scans through the target's tablegen instruction-info files 15 // and extracts instructions with obvious-looking patterns, and it emits 16 // code to look up these instructions by type and operator. 17 // 18 //===----------------------------------------------------------------------===// 19 20 #include "CodeGenDAGPatterns.h" 21 #include "llvm/ADT/SmallString.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/ErrorHandling.h" 24 #include "llvm/TableGen/Error.h" 25 #include "llvm/TableGen/Record.h" 26 #include "llvm/TableGen/TableGenBackend.h" 27 using namespace llvm; 28 29 30 /// InstructionMemo - This class holds additional information about an 31 /// instruction needed to emit code for it. 32 /// 33 namespace { 34 struct InstructionMemo { 35 std::string Name; 36 const CodeGenRegisterClass *RC; 37 std::string SubRegNo; 38 std::vector<std::string>* PhysRegs; 39 }; 40 } // End anonymous namespace 41 42 /// ImmPredicateSet - This uniques predicates (represented as a string) and 43 /// gives them unique (small) integer ID's that start at 0. 44 namespace { 45 class ImmPredicateSet { 46 DenseMap<TreePattern *, unsigned> ImmIDs; 47 std::vector<TreePredicateFn> PredsByName; 48 public: 49 50 unsigned getIDFor(TreePredicateFn Pred) { 51 unsigned &Entry = ImmIDs[Pred.getOrigPatFragRecord()]; 52 if (Entry == 0) { 53 PredsByName.push_back(Pred); 54 Entry = PredsByName.size(); 55 } 56 return Entry-1; 57 } 58 59 const TreePredicateFn &getPredicate(unsigned i) { 60 assert(i < PredsByName.size()); 61 return PredsByName[i]; 62 } 63 64 typedef std::vector<TreePredicateFn>::const_iterator iterator; 65 iterator begin() const { return PredsByName.begin(); } 66 iterator end() const { return PredsByName.end(); } 67 68 }; 69 } // End anonymous namespace 70 71 /// OperandsSignature - This class holds a description of a list of operand 72 /// types. It has utility methods for emitting text based on the operands. 73 /// 74 namespace { 75 struct OperandsSignature { 76 class OpKind { 77 enum { OK_Reg, OK_FP, OK_Imm, OK_Invalid = -1 }; 78 char Repr; 79 public: 80 81 OpKind() : Repr(OK_Invalid) {} 82 83 bool operator<(OpKind RHS) const { return Repr < RHS.Repr; } 84 bool operator==(OpKind RHS) const { return Repr == RHS.Repr; } 85 86 static OpKind getReg() { OpKind K; K.Repr = OK_Reg; return K; } 87 static OpKind getFP() { OpKind K; K.Repr = OK_FP; return K; } 88 static OpKind getImm(unsigned V) { 89 assert((unsigned)OK_Imm+V < 128 && 90 "Too many integer predicates for the 'Repr' char"); 91 OpKind K; K.Repr = OK_Imm+V; return K; 92 } 93 94 bool isReg() const { return Repr == OK_Reg; } 95 bool isFP() const { return Repr == OK_FP; } 96 bool isImm() const { return Repr >= OK_Imm; } 97 98 unsigned getImmCode() const { assert(isImm()); return Repr-OK_Imm; } 99 100 void printManglingSuffix(raw_ostream &OS, ImmPredicateSet &ImmPredicates, 101 bool StripImmCodes) const { 102 if (isReg()) 103 OS << 'r'; 104 else if (isFP()) 105 OS << 'f'; 106 else { 107 OS << 'i'; 108 if (!StripImmCodes) 109 if (unsigned Code = getImmCode()) 110 OS << "_" << ImmPredicates.getPredicate(Code-1).getFnName(); 111 } 112 } 113 }; 114 115 116 SmallVector<OpKind, 3> Operands; 117 118 bool operator<(const OperandsSignature &O) const { 119 return Operands < O.Operands; 120 } 121 bool operator==(const OperandsSignature &O) const { 122 return Operands == O.Operands; 123 } 124 125 bool empty() const { return Operands.empty(); } 126 127 bool hasAnyImmediateCodes() const { 128 for (unsigned i = 0, e = Operands.size(); i != e; ++i) 129 if (Operands[i].isImm() && Operands[i].getImmCode() != 0) 130 return true; 131 return false; 132 } 133 134 /// getWithoutImmCodes - Return a copy of this with any immediate codes forced 135 /// to zero. 136 OperandsSignature getWithoutImmCodes() const { 137 OperandsSignature Result; 138 for (unsigned i = 0, e = Operands.size(); i != e; ++i) 139 if (!Operands[i].isImm()) 140 Result.Operands.push_back(Operands[i]); 141 else 142 Result.Operands.push_back(OpKind::getImm(0)); 143 return Result; 144 } 145 146 void emitImmediatePredicate(raw_ostream &OS, ImmPredicateSet &ImmPredicates) { 147 bool EmittedAnything = false; 148 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 149 if (!Operands[i].isImm()) continue; 150 151 unsigned Code = Operands[i].getImmCode(); 152 if (Code == 0) continue; 153 154 if (EmittedAnything) 155 OS << " &&\n "; 156 157 TreePredicateFn PredFn = ImmPredicates.getPredicate(Code-1); 158 159 // Emit the type check. 160 OS << "VT == " 161 << getEnumName(PredFn.getOrigPatFragRecord()->getTree(0)->getType(0)) 162 << " && "; 163 164 165 OS << PredFn.getFnName() << "(imm" << i <<')'; 166 EmittedAnything = true; 167 } 168 } 169 170 /// initialize - Examine the given pattern and initialize the contents 171 /// of the Operands array accordingly. Return true if all the operands 172 /// are supported, false otherwise. 173 /// 174 bool initialize(TreePatternNode *InstPatNode, const CodeGenTarget &Target, 175 MVT::SimpleValueType VT, 176 ImmPredicateSet &ImmediatePredicates) { 177 if (InstPatNode->isLeaf()) 178 return false; 179 180 if (InstPatNode->getOperator()->getName() == "imm") { 181 Operands.push_back(OpKind::getImm(0)); 182 return true; 183 } 184 185 if (InstPatNode->getOperator()->getName() == "fpimm") { 186 Operands.push_back(OpKind::getFP()); 187 return true; 188 } 189 190 const CodeGenRegisterClass *DstRC = 0; 191 192 for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) { 193 TreePatternNode *Op = InstPatNode->getChild(i); 194 195 // Handle imm operands specially. 196 if (!Op->isLeaf() && Op->getOperator()->getName() == "imm") { 197 unsigned PredNo = 0; 198 if (!Op->getPredicateFns().empty()) { 199 TreePredicateFn PredFn = Op->getPredicateFns()[0]; 200 // If there is more than one predicate weighing in on this operand 201 // then we don't handle it. This doesn't typically happen for 202 // immediates anyway. 203 if (Op->getPredicateFns().size() > 1 || 204 !PredFn.isImmediatePattern()) 205 return false; 206 // Ignore any instruction with 'FastIselShouldIgnore', these are 207 // not needed and just bloat the fast instruction selector. For 208 // example, X86 doesn't need to generate code to match ADD16ri8 since 209 // ADD16ri will do just fine. 210 Record *Rec = PredFn.getOrigPatFragRecord()->getRecord(); 211 if (Rec->getValueAsBit("FastIselShouldIgnore")) 212 return false; 213 214 PredNo = ImmediatePredicates.getIDFor(PredFn)+1; 215 } 216 217 // Handle unmatched immediate sizes here. 218 //if (Op->getType(0) != VT) 219 // return false; 220 221 Operands.push_back(OpKind::getImm(PredNo)); 222 continue; 223 } 224 225 226 // For now, filter out any operand with a predicate. 227 // For now, filter out any operand with multiple values. 228 if (!Op->getPredicateFns().empty() || Op->getNumTypes() != 1) 229 return false; 230 231 if (!Op->isLeaf()) { 232 if (Op->getOperator()->getName() == "fpimm") { 233 Operands.push_back(OpKind::getFP()); 234 continue; 235 } 236 // For now, ignore other non-leaf nodes. 237 return false; 238 } 239 240 assert(Op->hasTypeSet(0) && "Type infererence not done?"); 241 242 // For now, all the operands must have the same type (if they aren't 243 // immediates). Note that this causes us to reject variable sized shifts 244 // on X86. 245 if (Op->getType(0) != VT) 246 return false; 247 248 DefInit *OpDI = dyn_cast<DefInit>(Op->getLeafValue()); 249 if (!OpDI) 250 return false; 251 Record *OpLeafRec = OpDI->getDef(); 252 253 // For now, the only other thing we accept is register operands. 254 const CodeGenRegisterClass *RC = 0; 255 if (OpLeafRec->isSubClassOf("RegisterOperand")) 256 OpLeafRec = OpLeafRec->getValueAsDef("RegClass"); 257 if (OpLeafRec->isSubClassOf("RegisterClass")) 258 RC = &Target.getRegisterClass(OpLeafRec); 259 else if (OpLeafRec->isSubClassOf("Register")) 260 RC = Target.getRegBank().getRegClassForRegister(OpLeafRec); 261 else 262 return false; 263 264 // For now, this needs to be a register class of some sort. 265 if (!RC) 266 return false; 267 268 // For now, all the operands must have the same register class or be 269 // a strict subclass of the destination. 270 if (DstRC) { 271 if (DstRC != RC && !DstRC->hasSubClass(RC)) 272 return false; 273 } else 274 DstRC = RC; 275 Operands.push_back(OpKind::getReg()); 276 } 277 return true; 278 } 279 280 void PrintParameters(raw_ostream &OS) const { 281 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 282 if (Operands[i].isReg()) { 283 OS << "unsigned Op" << i << ", bool Op" << i << "IsKill"; 284 } else if (Operands[i].isImm()) { 285 OS << "uint64_t imm" << i; 286 } else if (Operands[i].isFP()) { 287 OS << "const ConstantFP *f" << i; 288 } else { 289 llvm_unreachable("Unknown operand kind!"); 290 } 291 if (i + 1 != e) 292 OS << ", "; 293 } 294 } 295 296 void PrintArguments(raw_ostream &OS, 297 const std::vector<std::string> &PR) const { 298 assert(PR.size() == Operands.size()); 299 bool PrintedArg = false; 300 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 301 if (PR[i] != "") 302 // Implicit physical register operand. 303 continue; 304 305 if (PrintedArg) 306 OS << ", "; 307 if (Operands[i].isReg()) { 308 OS << "Op" << i << ", Op" << i << "IsKill"; 309 PrintedArg = true; 310 } else if (Operands[i].isImm()) { 311 OS << "imm" << i; 312 PrintedArg = true; 313 } else if (Operands[i].isFP()) { 314 OS << "f" << i; 315 PrintedArg = true; 316 } else { 317 llvm_unreachable("Unknown operand kind!"); 318 } 319 } 320 } 321 322 void PrintArguments(raw_ostream &OS) const { 323 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 324 if (Operands[i].isReg()) { 325 OS << "Op" << i << ", Op" << i << "IsKill"; 326 } else if (Operands[i].isImm()) { 327 OS << "imm" << i; 328 } else if (Operands[i].isFP()) { 329 OS << "f" << i; 330 } else { 331 llvm_unreachable("Unknown operand kind!"); 332 } 333 if (i + 1 != e) 334 OS << ", "; 335 } 336 } 337 338 339 void PrintManglingSuffix(raw_ostream &OS, const std::vector<std::string> &PR, 340 ImmPredicateSet &ImmPredicates, 341 bool StripImmCodes = false) const { 342 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 343 if (PR[i] != "") 344 // Implicit physical register operand. e.g. Instruction::Mul expect to 345 // select to a binary op. On x86, mul may take a single operand with 346 // the other operand being implicit. We must emit something that looks 347 // like a binary instruction except for the very inner FastEmitInst_* 348 // call. 349 continue; 350 Operands[i].printManglingSuffix(OS, ImmPredicates, StripImmCodes); 351 } 352 } 353 354 void PrintManglingSuffix(raw_ostream &OS, ImmPredicateSet &ImmPredicates, 355 bool StripImmCodes = false) const { 356 for (unsigned i = 0, e = Operands.size(); i != e; ++i) 357 Operands[i].printManglingSuffix(OS, ImmPredicates, StripImmCodes); 358 } 359 }; 360 } // End anonymous namespace 361 362 namespace { 363 class FastISelMap { 364 typedef std::map<std::string, InstructionMemo> PredMap; 365 typedef std::map<MVT::SimpleValueType, PredMap> RetPredMap; 366 typedef std::map<MVT::SimpleValueType, RetPredMap> TypeRetPredMap; 367 typedef std::map<std::string, TypeRetPredMap> OpcodeTypeRetPredMap; 368 typedef std::map<OperandsSignature, OpcodeTypeRetPredMap> 369 OperandsOpcodeTypeRetPredMap; 370 371 OperandsOpcodeTypeRetPredMap SimplePatterns; 372 373 std::map<OperandsSignature, std::vector<OperandsSignature> > 374 SignaturesWithConstantForms; 375 376 std::string InstNS; 377 ImmPredicateSet ImmediatePredicates; 378 public: 379 explicit FastISelMap(std::string InstNS); 380 381 void collectPatterns(CodeGenDAGPatterns &CGP); 382 void printImmediatePredicates(raw_ostream &OS); 383 void printFunctionDefinitions(raw_ostream &OS); 384 }; 385 } // End anonymous namespace 386 387 static std::string getOpcodeName(Record *Op, CodeGenDAGPatterns &CGP) { 388 return CGP.getSDNodeInfo(Op).getEnumName(); 389 } 390 391 static std::string getLegalCName(std::string OpName) { 392 std::string::size_type pos = OpName.find("::"); 393 if (pos != std::string::npos) 394 OpName.replace(pos, 2, "_"); 395 return OpName; 396 } 397 398 FastISelMap::FastISelMap(std::string instns) 399 : InstNS(instns) { 400 } 401 402 static std::string PhyRegForNode(TreePatternNode *Op, 403 const CodeGenTarget &Target) { 404 std::string PhysReg; 405 406 if (!Op->isLeaf()) 407 return PhysReg; 408 409 Record *OpLeafRec = cast<DefInit>(Op->getLeafValue())->getDef(); 410 if (!OpLeafRec->isSubClassOf("Register")) 411 return PhysReg; 412 413 PhysReg += cast<StringInit>(OpLeafRec->getValue("Namespace")->getValue()) 414 ->getValue(); 415 PhysReg += "::"; 416 PhysReg += Target.getRegBank().getReg(OpLeafRec)->getName(); 417 return PhysReg; 418 } 419 420 void FastISelMap::collectPatterns(CodeGenDAGPatterns &CGP) { 421 const CodeGenTarget &Target = CGP.getTargetInfo(); 422 423 // Determine the target's namespace name. 424 InstNS = Target.getInstNamespace() + "::"; 425 assert(InstNS.size() > 2 && "Can't determine target-specific namespace!"); 426 427 // Scan through all the patterns and record the simple ones. 428 for (CodeGenDAGPatterns::ptm_iterator I = CGP.ptm_begin(), 429 E = CGP.ptm_end(); I != E; ++I) { 430 const PatternToMatch &Pattern = *I; 431 432 // For now, just look at Instructions, so that we don't have to worry 433 // about emitting multiple instructions for a pattern. 434 TreePatternNode *Dst = Pattern.getDstPattern(); 435 if (Dst->isLeaf()) continue; 436 Record *Op = Dst->getOperator(); 437 if (!Op->isSubClassOf("Instruction")) 438 continue; 439 CodeGenInstruction &II = CGP.getTargetInfo().getInstruction(Op); 440 if (II.Operands.empty()) 441 continue; 442 443 // For now, ignore multi-instruction patterns. 444 bool MultiInsts = false; 445 for (unsigned i = 0, e = Dst->getNumChildren(); i != e; ++i) { 446 TreePatternNode *ChildOp = Dst->getChild(i); 447 if (ChildOp->isLeaf()) 448 continue; 449 if (ChildOp->getOperator()->isSubClassOf("Instruction")) { 450 MultiInsts = true; 451 break; 452 } 453 } 454 if (MultiInsts) 455 continue; 456 457 // For now, ignore instructions where the first operand is not an 458 // output register. 459 const CodeGenRegisterClass *DstRC = 0; 460 std::string SubRegNo; 461 if (Op->getName() != "EXTRACT_SUBREG") { 462 Record *Op0Rec = II.Operands[0].Rec; 463 if (Op0Rec->isSubClassOf("RegisterOperand")) 464 Op0Rec = Op0Rec->getValueAsDef("RegClass"); 465 if (!Op0Rec->isSubClassOf("RegisterClass")) 466 continue; 467 DstRC = &Target.getRegisterClass(Op0Rec); 468 if (!DstRC) 469 continue; 470 } else { 471 // If this isn't a leaf, then continue since the register classes are 472 // a bit too complicated for now. 473 if (!Dst->getChild(1)->isLeaf()) continue; 474 475 DefInit *SR = dyn_cast<DefInit>(Dst->getChild(1)->getLeafValue()); 476 if (SR) 477 SubRegNo = getQualifiedName(SR->getDef()); 478 else 479 SubRegNo = Dst->getChild(1)->getLeafValue()->getAsString(); 480 } 481 482 // Inspect the pattern. 483 TreePatternNode *InstPatNode = Pattern.getSrcPattern(); 484 if (!InstPatNode) continue; 485 if (InstPatNode->isLeaf()) continue; 486 487 // Ignore multiple result nodes for now. 488 if (InstPatNode->getNumTypes() > 1) continue; 489 490 Record *InstPatOp = InstPatNode->getOperator(); 491 std::string OpcodeName = getOpcodeName(InstPatOp, CGP); 492 MVT::SimpleValueType RetVT = MVT::isVoid; 493 if (InstPatNode->getNumTypes()) RetVT = InstPatNode->getType(0); 494 MVT::SimpleValueType VT = RetVT; 495 if (InstPatNode->getNumChildren()) { 496 assert(InstPatNode->getChild(0)->getNumTypes() == 1); 497 VT = InstPatNode->getChild(0)->getType(0); 498 } 499 500 // For now, filter out any instructions with predicates. 501 if (!InstPatNode->getPredicateFns().empty()) 502 continue; 503 504 // Check all the operands. 505 OperandsSignature Operands; 506 if (!Operands.initialize(InstPatNode, Target, VT, ImmediatePredicates)) 507 continue; 508 509 std::vector<std::string>* PhysRegInputs = new std::vector<std::string>(); 510 if (InstPatNode->getOperator()->getName() == "imm" || 511 InstPatNode->getOperator()->getName() == "fpimm") 512 PhysRegInputs->push_back(""); 513 else { 514 // Compute the PhysRegs used by the given pattern, and check that 515 // the mapping from the src to dst patterns is simple. 516 bool FoundNonSimplePattern = false; 517 unsigned DstIndex = 0; 518 for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) { 519 std::string PhysReg = PhyRegForNode(InstPatNode->getChild(i), Target); 520 if (PhysReg.empty()) { 521 if (DstIndex >= Dst->getNumChildren() || 522 Dst->getChild(DstIndex)->getName() != 523 InstPatNode->getChild(i)->getName()) { 524 FoundNonSimplePattern = true; 525 break; 526 } 527 ++DstIndex; 528 } 529 530 PhysRegInputs->push_back(PhysReg); 531 } 532 533 if (Op->getName() != "EXTRACT_SUBREG" && DstIndex < Dst->getNumChildren()) 534 FoundNonSimplePattern = true; 535 536 if (FoundNonSimplePattern) 537 continue; 538 } 539 540 // Get the predicate that guards this pattern. 541 std::string PredicateCheck = Pattern.getPredicateCheck(); 542 543 // Ok, we found a pattern that we can handle. Remember it. 544 InstructionMemo Memo = { 545 Pattern.getDstPattern()->getOperator()->getName(), 546 DstRC, 547 SubRegNo, 548 PhysRegInputs 549 }; 550 551 if (SimplePatterns[Operands][OpcodeName][VT][RetVT].count(PredicateCheck)) 552 PrintFatalError(Pattern.getSrcRecord()->getLoc(), 553 "Duplicate record in FastISel table!"); 554 555 SimplePatterns[Operands][OpcodeName][VT][RetVT][PredicateCheck] = Memo; 556 557 // If any of the operands were immediates with predicates on them, strip 558 // them down to a signature that doesn't have predicates so that we can 559 // associate them with the stripped predicate version. 560 if (Operands.hasAnyImmediateCodes()) { 561 SignaturesWithConstantForms[Operands.getWithoutImmCodes()] 562 .push_back(Operands); 563 } 564 } 565 } 566 567 void FastISelMap::printImmediatePredicates(raw_ostream &OS) { 568 if (ImmediatePredicates.begin() == ImmediatePredicates.end()) 569 return; 570 571 OS << "\n// FastEmit Immediate Predicate functions.\n"; 572 for (ImmPredicateSet::iterator I = ImmediatePredicates.begin(), 573 E = ImmediatePredicates.end(); I != E; ++I) { 574 OS << "static bool " << I->getFnName() << "(int64_t Imm) {\n"; 575 OS << I->getImmediatePredicateCode() << "\n}\n"; 576 } 577 578 OS << "\n\n"; 579 } 580 581 582 void FastISelMap::printFunctionDefinitions(raw_ostream &OS) { 583 // Now emit code for all the patterns that we collected. 584 for (OperandsOpcodeTypeRetPredMap::const_iterator OI = SimplePatterns.begin(), 585 OE = SimplePatterns.end(); OI != OE; ++OI) { 586 const OperandsSignature &Operands = OI->first; 587 const OpcodeTypeRetPredMap &OTM = OI->second; 588 589 for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end(); 590 I != E; ++I) { 591 const std::string &Opcode = I->first; 592 const TypeRetPredMap &TM = I->second; 593 594 OS << "// FastEmit functions for " << Opcode << ".\n"; 595 OS << "\n"; 596 597 // Emit one function for each opcode,type pair. 598 for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end(); 599 TI != TE; ++TI) { 600 MVT::SimpleValueType VT = TI->first; 601 const RetPredMap &RM = TI->second; 602 if (RM.size() != 1) { 603 for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end(); 604 RI != RE; ++RI) { 605 MVT::SimpleValueType RetVT = RI->first; 606 const PredMap &PM = RI->second; 607 bool HasPred = false; 608 609 OS << "unsigned FastEmit_" 610 << getLegalCName(Opcode) 611 << "_" << getLegalCName(getName(VT)) 612 << "_" << getLegalCName(getName(RetVT)) << "_"; 613 Operands.PrintManglingSuffix(OS, ImmediatePredicates); 614 OS << "("; 615 Operands.PrintParameters(OS); 616 OS << ") {\n"; 617 618 // Emit code for each possible instruction. There may be 619 // multiple if there are subtarget concerns. 620 for (PredMap::const_iterator PI = PM.begin(), PE = PM.end(); 621 PI != PE; ++PI) { 622 std::string PredicateCheck = PI->first; 623 const InstructionMemo &Memo = PI->second; 624 625 if (PredicateCheck.empty()) { 626 assert(!HasPred && 627 "Multiple instructions match, at least one has " 628 "a predicate and at least one doesn't!"); 629 } else { 630 OS << " if (" + PredicateCheck + ") {\n"; 631 OS << " "; 632 HasPred = true; 633 } 634 635 for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) { 636 if ((*Memo.PhysRegs)[i] != "") 637 OS << " BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, " 638 << "TII.get(TargetOpcode::COPY), " 639 << (*Memo.PhysRegs)[i] << ").addReg(Op" << i << ");\n"; 640 } 641 642 OS << " return FastEmitInst_"; 643 if (Memo.SubRegNo.empty()) { 644 Operands.PrintManglingSuffix(OS, *Memo.PhysRegs, 645 ImmediatePredicates, true); 646 OS << "(" << InstNS << Memo.Name << ", "; 647 OS << "&" << InstNS << Memo.RC->getName() << "RegClass"; 648 if (!Operands.empty()) 649 OS << ", "; 650 Operands.PrintArguments(OS, *Memo.PhysRegs); 651 OS << ");\n"; 652 } else { 653 OS << "extractsubreg(" << getName(RetVT); 654 OS << ", Op0, Op0IsKill, " << Memo.SubRegNo << ");\n"; 655 } 656 657 if (HasPred) 658 OS << " }\n"; 659 660 } 661 // Return 0 if none of the predicates were satisfied. 662 if (HasPred) 663 OS << " return 0;\n"; 664 OS << "}\n"; 665 OS << "\n"; 666 } 667 668 // Emit one function for the type that demultiplexes on return type. 669 OS << "unsigned FastEmit_" 670 << getLegalCName(Opcode) << "_" 671 << getLegalCName(getName(VT)) << "_"; 672 Operands.PrintManglingSuffix(OS, ImmediatePredicates); 673 OS << "(MVT RetVT"; 674 if (!Operands.empty()) 675 OS << ", "; 676 Operands.PrintParameters(OS); 677 OS << ") {\nswitch (RetVT.SimpleTy) {\n"; 678 for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end(); 679 RI != RE; ++RI) { 680 MVT::SimpleValueType RetVT = RI->first; 681 OS << " case " << getName(RetVT) << ": return FastEmit_" 682 << getLegalCName(Opcode) << "_" << getLegalCName(getName(VT)) 683 << "_" << getLegalCName(getName(RetVT)) << "_"; 684 Operands.PrintManglingSuffix(OS, ImmediatePredicates); 685 OS << "("; 686 Operands.PrintArguments(OS); 687 OS << ");\n"; 688 } 689 OS << " default: return 0;\n}\n}\n\n"; 690 691 } else { 692 // Non-variadic return type. 693 OS << "unsigned FastEmit_" 694 << getLegalCName(Opcode) << "_" 695 << getLegalCName(getName(VT)) << "_"; 696 Operands.PrintManglingSuffix(OS, ImmediatePredicates); 697 OS << "(MVT RetVT"; 698 if (!Operands.empty()) 699 OS << ", "; 700 Operands.PrintParameters(OS); 701 OS << ") {\n"; 702 703 OS << " if (RetVT.SimpleTy != " << getName(RM.begin()->first) 704 << ")\n return 0;\n"; 705 706 const PredMap &PM = RM.begin()->second; 707 bool HasPred = false; 708 709 // Emit code for each possible instruction. There may be 710 // multiple if there are subtarget concerns. 711 for (PredMap::const_iterator PI = PM.begin(), PE = PM.end(); PI != PE; 712 ++PI) { 713 std::string PredicateCheck = PI->first; 714 const InstructionMemo &Memo = PI->second; 715 716 if (PredicateCheck.empty()) { 717 assert(!HasPred && 718 "Multiple instructions match, at least one has " 719 "a predicate and at least one doesn't!"); 720 } else { 721 OS << " if (" + PredicateCheck + ") {\n"; 722 OS << " "; 723 HasPred = true; 724 } 725 726 for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) { 727 if ((*Memo.PhysRegs)[i] != "") 728 OS << " BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, " 729 << "TII.get(TargetOpcode::COPY), " 730 << (*Memo.PhysRegs)[i] << ").addReg(Op" << i << ");\n"; 731 } 732 733 OS << " return FastEmitInst_"; 734 735 if (Memo.SubRegNo.empty()) { 736 Operands.PrintManglingSuffix(OS, *Memo.PhysRegs, 737 ImmediatePredicates, true); 738 OS << "(" << InstNS << Memo.Name << ", "; 739 OS << "&" << InstNS << Memo.RC->getName() << "RegClass"; 740 if (!Operands.empty()) 741 OS << ", "; 742 Operands.PrintArguments(OS, *Memo.PhysRegs); 743 OS << ");\n"; 744 } else { 745 OS << "extractsubreg(RetVT, Op0, Op0IsKill, "; 746 OS << Memo.SubRegNo; 747 OS << ");\n"; 748 } 749 750 if (HasPred) 751 OS << " }\n"; 752 } 753 754 // Return 0 if none of the predicates were satisfied. 755 if (HasPred) 756 OS << " return 0;\n"; 757 OS << "}\n"; 758 OS << "\n"; 759 } 760 } 761 762 // Emit one function for the opcode that demultiplexes based on the type. 763 OS << "unsigned FastEmit_" 764 << getLegalCName(Opcode) << "_"; 765 Operands.PrintManglingSuffix(OS, ImmediatePredicates); 766 OS << "(MVT VT, MVT RetVT"; 767 if (!Operands.empty()) 768 OS << ", "; 769 Operands.PrintParameters(OS); 770 OS << ") {\n"; 771 OS << " switch (VT.SimpleTy) {\n"; 772 for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end(); 773 TI != TE; ++TI) { 774 MVT::SimpleValueType VT = TI->first; 775 std::string TypeName = getName(VT); 776 OS << " case " << TypeName << ": return FastEmit_" 777 << getLegalCName(Opcode) << "_" << getLegalCName(TypeName) << "_"; 778 Operands.PrintManglingSuffix(OS, ImmediatePredicates); 779 OS << "(RetVT"; 780 if (!Operands.empty()) 781 OS << ", "; 782 Operands.PrintArguments(OS); 783 OS << ");\n"; 784 } 785 OS << " default: return 0;\n"; 786 OS << " }\n"; 787 OS << "}\n"; 788 OS << "\n"; 789 } 790 791 OS << "// Top-level FastEmit function.\n"; 792 OS << "\n"; 793 794 // Emit one function for the operand signature that demultiplexes based 795 // on opcode and type. 796 OS << "unsigned FastEmit_"; 797 Operands.PrintManglingSuffix(OS, ImmediatePredicates); 798 OS << "(MVT VT, MVT RetVT, unsigned Opcode"; 799 if (!Operands.empty()) 800 OS << ", "; 801 Operands.PrintParameters(OS); 802 OS << ") {\n"; 803 804 // If there are any forms of this signature available that operand on 805 // constrained forms of the immediate (e.g. 32-bit sext immediate in a 806 // 64-bit operand), check them first. 807 808 std::map<OperandsSignature, std::vector<OperandsSignature> >::iterator MI 809 = SignaturesWithConstantForms.find(Operands); 810 if (MI != SignaturesWithConstantForms.end()) { 811 // Unique any duplicates out of the list. 812 std::sort(MI->second.begin(), MI->second.end()); 813 MI->second.erase(std::unique(MI->second.begin(), MI->second.end()), 814 MI->second.end()); 815 816 // Check each in order it was seen. It would be nice to have a good 817 // relative ordering between them, but we're not going for optimality 818 // here. 819 for (unsigned i = 0, e = MI->second.size(); i != e; ++i) { 820 OS << " if ("; 821 MI->second[i].emitImmediatePredicate(OS, ImmediatePredicates); 822 OS << ")\n if (unsigned Reg = FastEmit_"; 823 MI->second[i].PrintManglingSuffix(OS, ImmediatePredicates); 824 OS << "(VT, RetVT, Opcode"; 825 if (!MI->second[i].empty()) 826 OS << ", "; 827 MI->second[i].PrintArguments(OS); 828 OS << "))\n return Reg;\n\n"; 829 } 830 831 // Done with this, remove it. 832 SignaturesWithConstantForms.erase(MI); 833 } 834 835 OS << " switch (Opcode) {\n"; 836 for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end(); 837 I != E; ++I) { 838 const std::string &Opcode = I->first; 839 840 OS << " case " << Opcode << ": return FastEmit_" 841 << getLegalCName(Opcode) << "_"; 842 Operands.PrintManglingSuffix(OS, ImmediatePredicates); 843 OS << "(VT, RetVT"; 844 if (!Operands.empty()) 845 OS << ", "; 846 Operands.PrintArguments(OS); 847 OS << ");\n"; 848 } 849 OS << " default: return 0;\n"; 850 OS << " }\n"; 851 OS << "}\n"; 852 OS << "\n"; 853 } 854 855 // TODO: SignaturesWithConstantForms should be empty here. 856 } 857 858 namespace llvm { 859 860 void EmitFastISel(RecordKeeper &RK, raw_ostream &OS) { 861 CodeGenDAGPatterns CGP(RK); 862 const CodeGenTarget &Target = CGP.getTargetInfo(); 863 emitSourceFileHeader("\"Fast\" Instruction Selector for the " + 864 Target.getName() + " target", OS); 865 866 // Determine the target's namespace name. 867 std::string InstNS = Target.getInstNamespace() + "::"; 868 assert(InstNS.size() > 2 && "Can't determine target-specific namespace!"); 869 870 FastISelMap F(InstNS); 871 F.collectPatterns(CGP); 872 F.printImmediatePredicates(OS); 873 F.printFunctionDefinitions(OS); 874 } 875 876 } // End llvm namespace 877
