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    Searched defs:SubRegs (Results 1 - 4 of 4) sorted by null

  /external/llvm/include/llvm/MC/
MCRegisterInfo.h 106 /// alias EAX. The SubRegs field is a zero terminated array of registers that
115 uint32_t SubRegs; // Sub-register set, described above
119 // sub-register in SubRegs.
427 init(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs);
  /external/llvm/utils/TableGen/
CodeGenRegisters.h 126 return SubRegs;
222 SubRegMap SubRegs;
CodeGenRegisters.cpp 113 std::vector<Record*> SRs = TheDef->getValueAsListOfDefs("SubRegs");
117 "SubRegs and SubRegIndices must have the same size");
125 // covered-by-subregs super-registers where it appears as the first explicit
207 for (SubRegMap::const_iterator I = SubRegs.begin(), E = SubRegs.end();
220 return SubRegs;
223 // First insert the explicit subregs and make sure they are fully indexed.
227 if (!SubRegs.insert(std::make_pair(Idx, SR)).second)
235 // Keep track of inherited subregs and how they can be reached.
238 // Clone inherited subregs and place duplicate entries in Orphans
    [all...]
  /external/llvm/lib/Target/ARM/
ARMBaseInstrInfo.cpp 691 unsigned SubRegs = 0;
696 Opc = ARM::VORRq, BeginIdx = ARM::qsub_0, SubRegs = 2;
698 Opc = ARM::VORRq, BeginIdx = ARM::qsub_0, SubRegs = 4;
701 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 2;
703 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 3;
705 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 4;
707 Opc = ARM::MOVr, BeginIdx = ARM::gsub_0, SubRegs = 2;
710 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 2, Spacing = 2;
712 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 3, Spacing = 2;
714 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 4, Spacing = 2
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