1 /* 2 * Copyright 2009-2011 Oleg Mazurov, Circuits At Home, http://www.circuitsathome.com 3 * MAX3421E USB host controller support 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. Neither the name of the authors nor the names of its contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* MAX3421E register/bit names and bitmasks */ 31 32 #ifndef _MAX3421Econstants_h_ 33 #define _MAX3421Econstants_h_ 34 35 /* SPI pins for diffrent Arduinos */ 36 37 #if defined(__AVR_ATmega1280__) || (__AVR_ATmega2560__) 38 #define SCK_PIN 52 39 #define MISO_PIN 50 40 #define MOSI_PIN 51 41 #define SS_PIN 53 42 #endif 43 #if defined(__AVR_ATmega168__) || defined(__AVR_ATmega328P__) 44 #define SCK_PIN 13 45 #define MISO_PIN 12 46 #define MOSI_PIN 11 47 #define SS_PIN 10 48 #endif 49 50 #define MAX_SS 53 51 #define MAX_INT 9 52 #define MAX_GPX 8 53 #define MAX_RESET 7 54 55 /* "Breakpoint" pins for debugging */ 56 //#define BPNT_0 3 57 //#define BPNT_1 2 58 59 //#define Select_MAX3421E digitalWrite(MAX_SS,LOW) 60 //#define Deselect_MAX3421E digitalWrite(MAX_SS,HIGH) 61 62 /* */ 63 64 #define ON true 65 #define OFF false 66 67 /* VBUS states */ 68 #define SE0 0 69 #define SE1 1 70 #define FSHOST 2 71 #define LSHOST 3 72 73 /* MAX3421E command byte format: rrrrr0wa where 'r' is register number */ 74 // 75 // MAX3421E Registers in HOST mode. 76 // 77 #define rRCVFIFO 0x08 //1<<3 78 #define rSNDFIFO 0x10 //2<<3 79 #define rSUDFIFO 0x20 //4<<3 80 #define rRCVBC 0x30 //6<<3 81 #define rSNDBC 0x38 //7<<3 82 83 #define rUSBIRQ 0x68 //13<<3 84 /* USBIRQ Bits */ 85 #define bmVBUSIRQ 0x40 //b6 86 #define bmNOVBUSIRQ 0x20 //b5 87 #define bmOSCOKIRQ 0x01 //b0 88 89 #define rUSBIEN 0x70 //14<<3 90 /* USBIEN Bits */ 91 #define bmVBUSIE 0x40 //b6 92 #define bmNOVBUSIE 0x20 //b5 93 #define bmOSCOKIE 0x01 //b0 94 95 #define rUSBCTL 0x78 //15<<3 96 /* USBCTL Bits */ 97 #define bmCHIPRES 0x20 //b5 98 #define bmPWRDOWN 0x10 //b4 99 100 #define rCPUCTL 0x80 //16<<3 101 /* CPUCTL Bits */ 102 #define bmPUSLEWID1 0x80 //b7 103 #define bmPULSEWID0 0x40 //b6 104 #define bmIE 0x01 //b0 105 106 #define rPINCTL 0x88 //17<<3 107 /* PINCTL Bits */ 108 #define bmFDUPSPI 0x10 //b4 109 #define bmINTLEVEL 0x08 //b3 110 #define bmPOSINT 0x04 //b2 111 #define bmGPXB 0x02 //b1 112 #define bmGPXA 0x01 //b0 113 // GPX pin selections 114 #define GPX_OPERATE 0x00 115 #define GPX_VBDET 0x01 116 #define GPX_BUSACT 0x02 117 #define GPX_SOF 0x03 118 119 #define rREVISION 0x90 //18<<3 120 121 #define rIOPINS1 0xa0 //20<<3 122 123 /* IOPINS1 Bits */ 124 #define bmGPOUT0 0x01 125 #define bmGPOUT1 0x02 126 #define bmGPOUT2 0x04 127 #define bmGPOUT3 0x08 128 #define bmGPIN0 0x10 129 #define bmGPIN1 0x20 130 #define bmGPIN2 0x40 131 #define bmGPIN3 0x80 132 133 #define rIOPINS2 0xa8 //21<<3 134 /* IOPINS2 Bits */ 135 #define bmGPOUT4 0x01 136 #define bmGPOUT5 0x02 137 #define bmGPOUT6 0x04 138 #define bmGPOUT7 0x08 139 #define bmGPIN4 0x10 140 #define bmGPIN5 0x20 141 #define bmGPIN6 0x40 142 #define bmGPIN7 0x80 143 144 #define rGPINIRQ 0xb0 //22<<3 145 /* GPINIRQ Bits */ 146 #define bmGPINIRQ0 0x01 147 #define bmGPINIRQ1 0x02 148 #define bmGPINIRQ2 0x04 149 #define bmGPINIRQ3 0x08 150 #define bmGPINIRQ4 0x10 151 #define bmGPINIRQ5 0x20 152 #define bmGPINIRQ6 0x40 153 #define bmGPINIRQ7 0x80 154 155 #define rGPINIEN 0xb8 //23<<3 156 /* GPINIEN Bits */ 157 #define bmGPINIEN0 0x01 158 #define bmGPINIEN1 0x02 159 #define bmGPINIEN2 0x04 160 #define bmGPINIEN3 0x08 161 #define bmGPINIEN4 0x10 162 #define bmGPINIEN5 0x20 163 #define bmGPINIEN6 0x40 164 #define bmGPINIEN7 0x80 165 166 #define rGPINPOL 0xc0 //24<<3 167 /* GPINPOL Bits */ 168 #define bmGPINPOL0 0x01 169 #define bmGPINPOL1 0x02 170 #define bmGPINPOL2 0x04 171 #define bmGPINPOL3 0x08 172 #define bmGPINPOL4 0x10 173 #define bmGPINPOL5 0x20 174 #define bmGPINPOL6 0x40 175 #define bmGPINPOL7 0x80 176 177 #define rHIRQ 0xc8 //25<<3 178 /* HIRQ Bits */ 179 #define bmBUSEVENTIRQ 0x01 // indicates BUS Reset Done or BUS Resume 180 #define bmRWUIRQ 0x02 181 #define bmRCVDAVIRQ 0x04 182 #define bmSNDBAVIRQ 0x08 183 #define bmSUSDNIRQ 0x10 184 #define bmCONDETIRQ 0x20 185 #define bmFRAMEIRQ 0x40 186 #define bmHXFRDNIRQ 0x80 187 188 #define rHIEN 0xd0 //26<<3 189 /* HIEN Bits */ 190 #define bmBUSEVENTIE 0x01 191 #define bmRWUIE 0x02 192 #define bmRCVDAVIE 0x04 193 #define bmSNDBAVIE 0x08 194 #define bmSUSDNIE 0x10 195 #define bmCONDETIE 0x20 196 #define bmFRAMEIE 0x40 197 #define bmHXFRDNIE 0x80 198 199 #define rMODE 0xd8 //27<<3 200 /* MODE Bits */ 201 #define bmHOST 0x01 202 #define bmLOWSPEED 0x02 203 #define bmHUBPRE 0x04 204 #define bmSOFKAENAB 0x08 205 #define bmSEPIRQ 0x10 206 #define bmDELAYISO 0x20 207 #define bmDMPULLDN 0x40 208 #define bmDPPULLDN 0x80 209 210 #define rPERADDR 0xe0 //28<<3 211 212 #define rHCTL 0xe8 //29<<3 213 /* HCTL Bits */ 214 #define bmBUSRST 0x01 215 #define bmFRMRST 0x02 216 #define bmSAMPLEBUS 0x04 217 #define bmSIGRSM 0x08 218 #define bmRCVTOG0 0x10 219 #define bmRCVTOG1 0x20 220 #define bmSNDTOG0 0x40 221 #define bmSNDTOG1 0x80 222 223 #define rHXFR 0xf0 //30<<3 224 /* Host transfer token values for writing the HXFR register (R30) */ 225 /* OR this bit field with the endpoint number in bits 3:0 */ 226 #define tokSETUP 0x10 // HS=0, ISO=0, OUTNIN=0, SETUP=1 227 #define tokIN 0x00 // HS=0, ISO=0, OUTNIN=0, SETUP=0 228 #define tokOUT 0x20 // HS=0, ISO=0, OUTNIN=1, SETUP=0 229 #define tokINHS 0x80 // HS=1, ISO=0, OUTNIN=0, SETUP=0 230 #define tokOUTHS 0xA0 // HS=1, ISO=0, OUTNIN=1, SETUP=0 231 #define tokISOIN 0x40 // HS=0, ISO=1, OUTNIN=0, SETUP=0 232 #define tokISOOUT 0x60 // HS=0, ISO=1, OUTNIN=1, SETUP=0 233 234 #define rHRSL 0xf8 //31<<3 235 /* HRSL Bits */ 236 #define bmRCVTOGRD 0x10 237 #define bmSNDTOGRD 0x20 238 #define bmKSTATUS 0x40 239 #define bmJSTATUS 0x80 240 #define bmSE0 0x00 //SE0 - disconnect state 241 #define bmSE1 0xc0 //SE1 - illegal state 242 /* Host error result codes, the 4 LSB's in the HRSL register */ 243 #define hrSUCCESS 0x00 244 #define hrBUSY 0x01 245 #define hrBADREQ 0x02 246 #define hrUNDEF 0x03 247 #define hrNAK 0x04 248 #define hrSTALL 0x05 249 #define hrTOGERR 0x06 250 #define hrWRONGPID 0x07 251 #define hrBADBC 0x08 252 #define hrPIDERR 0x09 253 #define hrPKTERR 0x0A 254 #define hrCRCERR 0x0B 255 #define hrKERR 0x0C 256 #define hrJERR 0x0D 257 #define hrTIMEOUT 0x0E 258 #define hrBABBLE 0x0F 259 260 #define MODE_FS_HOST (bmDPPULLDN|bmDMPULLDN|bmHOST|bmSOFKAENAB) 261 #define MODE_LS_HOST (bmDPPULLDN|bmDMPULLDN|bmHOST|bmLOWSPEED|bmSOFKAENAB) 262 263 264 #endif //_MAX3421Econstants_h_ 265
