| /external/qemu/target-mips/ |
| helper.c | 291 } lui, lw, srl; member in struct:__anon13958
295 {0x00, 0x3c1b0000, 0xffff0000}, /* 0x3c1b803f : lui k1,%hi(pgd_current_p) */
301 {0x00, 0x3c1b0000, 0xffff0000}, /* 0x3c1b803f : lui k1,%hi(pgd_current_p) */
311 lui_ins = ldl_phys(ebase + handlers[i].lui.off);
314 if (((lui_ins & handlers[i].lui.mask) == handlers[i].lui.op) &&
|
| /external/webkit/Source/JavaScriptCore/assembler/ |
| MIPSAssembler.h | 257 lui(dest, imm >> 16);
263 void lui(RegisterID rt, int imm) function in class:JSC::MIPSAssembler
771 ASSERT((*insn & 0xffe00000) == 0x3c000000); // lui
804 ASSERT((*insn & 0xffe00000) == 0x3c000000); // lui
841 /* lui */
848 } else if ((*insn & 0xffe00000) == 0x3c000000) { // lui
853 /* lui */
893 lui $25, target >> 16
924 /* lui */
949 /* lui $25, (to >> 16) & 0xffff *
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| /external/v8/src/mips/ |
| assembler-mips.cc | 182 // specially coded on MIPS means that it is a lui/ori instruction, and that is
567 return opcode == LUI;
1449 void Assembler::lui(Register rd, int32_t j) { function in class:v8::Assembler
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