/system/core/libpixelflinger/codeflinger/ |
MIPSAssembler.cpp | 166 mMips->ADDIU(R_sp, R_sp, -(5 * 4)); 184 mMips->ADDIU(R_sp, R_sp, (5 * 4)); 446 mMips->ADDIU(Rd, Rn, src); 784 mMips->ADDIU(Rn, Rn, amode.value); 792 mMips->ADDIU(Rn, Rn, amode.value); 815 mMips->ADDIU(Rn, Rn, amode.value); 820 mMips->ADDIU(Rn, Rn, amode.value); 848 mMips->ADDIU(Rn, Rn, amode.value); 857 mMips->ADDIU(Rn, Rn, amode.value); // post index always writes back 880 mMips->ADDIU(Rn, Rn, amode.value) [all...] |
MIPSAssembler.h | 273 void ADDIU(int Rt, int Rs, int16_t imm);
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/external/v8/src/mips/ |
constants-mips.cc | 312 case ADDIU:
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constants-mips.h | 264 ADDIU = ((1 << 3) + 1) << kOpcodeShift, 568 // addiu(sp, sp, 4) aka Pop() operation or part of Pop(r) 571 // addiu(sp, sp, -4) part of Push(r) operation as pre-decrement of sp.
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assembler-mips.cc | 238 // addiu(sp, sp, 4) aka Pop() operation or part of Pop(r) 240 const Instr kPopInstruction = ADDIU | (kRegister_sp_Code << kRsShift) 242 // addiu(sp, sp, -4) part of Push(r) operation as pre-decrement of sp. 243 const Instr kPushInstruction = ADDIU | (kRegister_sp_Code << kRsShift) 639 return ((instr & kOpcodeMask) == ADDIU); 1204 void Assembler::addiu(Register rd, Register rs, int32_t j) { function in class:v8::Assembler [all...] |
simulator-mips.cc | [all...] |
/external/valgrind/main/none/tests/mips32/ |
MIPS32int.stdout.exp | 24 ADDIU 25 addiu $t0, $t1, 0 :: rt 0x00000000 rs 0x00000000, imm 0x00000000 26 addiu $t0, $t1, 1 :: rt 0x00000001 rs 0x00000000, imm 0x00000001 27 addiu $t0, $t1, 1 :: rt 0x00000002 rs 0x00000001, imm 0x00000000 28 addiu $t0, $t1, 1 :: rt 0x00000002 rs 0x00000001, imm 0x00000001 29 addiu $t0, $t1, -1 :: rt 0xffffffff rs 0x00000000, imm 0xffffffff 30 addiu $t0, $t1, -1 :: rt 0x00000000 rs 0x00000001, imm 0xffffffff 31 addiu $t0, $t1, 0 :: rt 0x80000000 rs 0x80000000, imm 0x00000000 32 addiu $t0, $t1, 0 :: rt 0xffffffff rs 0xffffffff, imm 0x00000000 33 addiu $t0, $t1, 0 :: rt 0x80000000 rs 0x80000000, imm 0x0000000 [all...] |