| /external/llvm/lib/Transforms/Scalar/ |
| CodeGenPrepare.cpp | 824 /// ExtAddrMode - This is an extended version of TargetLowering::AddrMode
826 struct ExtAddrMode : public TargetLowering::AddrMode {
894 /// AddrMode - This is the addressing mode that we're building up. This is
896 ExtAddrMode &AddrMode;
906 : AddrModeInsts(AMI), TLI(T), AccessTy(AT), MemoryInst(MI), AddrMode(AM) {
[all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb2InstrInfo.cpp | 393 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
398 AddrMode = ARMII::AddrModeT2_i12; // FIXME. mode for thumb2?
468 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
474 if (AddrMode == ARMII::AddrModeT2_so) {
484 AddrMode = ARMII::AddrModeT2_i12;
489 if (AddrMode == ARMII::AddrModeT2_i8 || AddrMode == ARMII::AddrModeT2_i12) {
503 } else if (AddrMode == ARMII::AddrMode5) {
534 if (AddrMode == ARMII::AddrMode5
[all...] |
| ARMBaseRegisterInfo.cpp | 407 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
411 switch (AddrMode) {
596 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
605 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
611 switch (AddrMode) {
|
| ARMISelLowering.h | 303 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
304 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
|
| Thumb1RegisterInfo.cpp | 355 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
439 if (AddrMode != ARMII::AddrModeT1_s)
646 // Use [reg, reg] addrmode. Replace the immediate operand w/ the frame
668 // Use [reg, reg] addrmode. Replace the immediate operand w/ the frame
|
| ARMBaseInstrInfo.cpp | 151 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
163 switch (AddrMode) {
[all...] |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonBaseInfo.h | 62 enum AddrMode {
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMBaseInfo.h | 191 enum AddrMode {
211 inline static const char *AddrModeToString(AddrMode addrmode) {
212 switch (addrmode) {
282 AddrModeMask = 0x1f, // The AddrMode enums are declared in ARMBaseInfo.h
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.h | 162 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
|
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.h | 98 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
|
| NVPTXISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.h | 106 virtual bool isLegalAddressingMode(const AddrMode &AM,
|
| XCoreISelLowering.cpp | [all...] |
| /external/v8/src/arm/ |
| assembler-arm.h | 459 explicit MemOperand(Register rn, int32_t offset = 0, AddrMode am = Offset);
464 explicit MemOperand(Register rn, Register rm, AddrMode am = Offset);
470 ShiftOp shift_op, int shift_imm, AddrMode am = Offset);
484 AddrMode am() const { return am_; }
496 AddrMode am_; // bits P, U, and W
[all...] |
| constants-arm.h | 318 enum AddrMode {
|
| assembler-arm.cc | 208 MemOperand::MemOperand(Register rn, int32_t offset, AddrMode am) {
215 MemOperand::MemOperand(Register rn, Register rm, AddrMode am) {
225 ShiftOp shift_op, int shift_imm, AddrMode am) {
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetLowering.h | [all...] |
| /external/llvm/lib/CodeGen/ |
| BasicTargetTransformInfo.cpp | 132 TargetLoweringBase::AddrMode AM;
|
| TargetLoweringBase.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.h | 420 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
|
| MipsISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.h | 423 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
|
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.h | 610 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
[all...] |
