| /dalvik/vm/mterp/x86/ |
| OP_MOVE_WIDE_16.S | 4 movzwl 4(rPC),%ecx # ecx<- BBBB
6 GET_VREG_WORD rINST %ecx 0 # rINSTw_WORD<- v[BBBB+0]
7 GET_VREG_WORD %ecx %ecx 1 # ecx<- v[BBBB+1]
|
| OP_MOVE_WIDE_FROM16.S | 4 movzwl 2(rPC),%ecx # ecx<- BBBB
6 GET_VREG_WORD rINST %ecx 0 # rINST<- v[BBBB+0]
7 GET_VREG_WORD %ecx %ecx 1 # ecx<- v[BBBB+1]
|
| OP_MOVE_FROM16.S | 5 movw 2(rPC),rINSTw # rINSTw <= BBBB
6 GET_VREG_R rINST rINST # rINST- fp[BBBB]
|
| OP_CONST_HIGH16.S | 3 movzwl 2(rPC),%eax # eax<- 0000BBBB
|
| OP_CONST_CLASS.S | 5 /* const/class vAA, Class@BBBB */
7 movzwl 2(rPC),%eax # eax<- BBBB
10 movl (%ecx,%eax,4),%eax # eax<- rResClasses[BBBB]
14 SET_VREG %eax rINST # vAA<- rResClasses[BBBB]
25 movzwl 2(rPC),%ecx # ecx<- BBBB
|
| OP_CONST_STRING.S | 5 /* const/string vAA, String@BBBB */
7 movzwl 2(rPC),%eax # eax<- BBBB
10 movl (%ecx,%eax,4),%eax # eax<- rResString[BBBB]
14 SET_VREG %eax rINST # vAA<- rResString[BBBB]
24 movzwl 2(rPC),%ecx # ecx<- BBBB
|
| OP_MOVE_16.S | 4 movzwl 4(rPC),%ecx # ecx<- BBBB
|
| OP_THROW_VERIFICATION_ERROR.S | 5 * exception is indicated by AA, with some detail provided by BBBB.
7 /* op AA, ref@BBBB */
9 movzwl 2(rPC),%eax # eax<- BBBB
12 movl %eax,OUT_ARG2(%esp) # arg2<- BBBB
|
| OP_CONST_WIDE_HIGH16.S | 3 movzwl 2(rPC),%eax # eax<- 0000BBBB
|
| OP_INVOKE_VIRTUAL_QUICK.S | 10 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
12 movzwl 2(rPC),%edx # ecx<- BBBB
22 movl (%eax,%edx,4),%eax # eax<- vtable[BBBB]
|
| /dalvik/vm/mterp/armv5te/ |
| OP_MOVE_16.S | 4 FETCH(r1, 2) @ r1<- BBBB
7 GET_VREG(r2, r1) @ r2<- fp[BBBB]
|
| OP_MOVE_FROM16.S | 4 FETCH(r1, 1) @ r1<- BBBB
7 GET_VREG(r2, r1) @ r2<- fp[BBBB]
|
| OP_MOVE_WIDE_16.S | 4 FETCH(r3, 2) @ r3<- BBBB
6 add r3, rFP, r3, lsl #2 @ r3<- &fp[BBBB]
8 ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB]
|
| OP_MOVE_WIDE_FROM16.S | 4 FETCH(r3, 1) @ r3<- BBBB
6 add r3, rFP, r3, lsl #2 @ r3<- &fp[BBBB]
8 ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB]
|
| OP_THROW_VERIFICATION_ERROR.S | 5 * exception is indicated by AA, with some detail provided by BBBB.
7 /* op AA, ref@BBBB */
9 FETCH(r2, 1) @ r2<- BBBB
|
| OP_INVOKE_VIRTUAL_QUICK.S | 10 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
12 FETCH(r1, 1) @ r1<- BBBB
22 ldr r0, [r2, r1, lsl #2] @ r3<- vtable[BBBB]
|
| OP_INVOKE_SUPER_QUICK.S | 10 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
16 FETCH(r1, 1) @ r1<- BBBB
23 ldr r0, [r2, r1, lsl #2] @ r0<- super->vtable[BBBB]
|
| /dalvik/vm/mterp/mips/ |
| OP_MOVE_16.S | 4 FETCH(a1, 2) # a1 <- BBBB
7 GET_VREG(a2, a1) # a2 <- fp[BBBB]
|
| OP_MOVE_FROM16.S | 4 FETCH(a1, 1) # a1 <- BBBB
7 GET_VREG(a2, a1) # a2 <- fp[BBBB]
|
| OP_MOVE_WIDE_16.S | 4 FETCH(a3, 2) # a3 <- BBBB
6 EAS2(a3, rFP, a3) # a3 <- &fp[BBBB]
8 LOAD64(a0, a1, a3) # a0/a1 <- fp[BBBB]
|
| OP_MOVE_WIDE_FROM16.S | 4 FETCH(a3, 1) # a3 <- BBBB
6 EAS2(a3, rFP, a3) # a3 <- &fp[BBBB]
8 LOAD64(a0, a1, a3) # a0/a1 <- fp[BBBB]
|
| OP_THROW_VERIFICATION_ERROR.S | 5 * exception is indicated by AA, with some detail provided by BBBB.
7 /* op AA, ref@BBBB */
10 FETCH(a2, 1) # a2 <- BBBB
|
| OP_CONST_HIGH16.S | 3 FETCH(a0, 1) # a0 <- 0000BBBB (zero-extended)
|
| OP_NEW_INSTANCE.S | 12 # new-instance vAA, class /* BBBB */
14 FETCH(a1, 1) # a1 <- BBBB
96 * a1 holds BBBB
|
| OP_INVOKE_VIRTUAL_QUICK.S | 10 # op vAA, {vCCCC..v(CCCC+AA-1)}, meth /* BBBB */
12 FETCH(a1, 1) # a1 <- BBBB
22 LOAD_eas2(a0, a2, a1) # a0 <- vtable[BBBB]
|
