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    Searched refs:BuildMI (Results 1 - 25 of 107) sorted by null

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/external/llvm/lib/Target/NVPTX/
NVPTXFrameLowering.cpp	45 MachineInstr *MI = BuildMI(MBB, MBBI, dl, 48 BuildMI(MBB, MI, dl, 52 MachineInstr *MI = BuildMI(MBB, MBBI, dl, 55 BuildMI(MBB, MI, dl, 63 BuildMI(MBB, MBBI, dl, 67 BuildMI(MBB, MBBI, dl,
NVPTXInstrInfo.cpp	42 BuildMI(MBB, I, DL, get(NVPTX::IMOV32rr), DestReg) 46 BuildMI(MBB, I, DL, get(NVPTX::IMOV8rr), DestReg) 50 BuildMI(MBB, I, DL, get(NVPTX::IMOV1rr), DestReg) 54 BuildMI(MBB, I, DL, get(NVPTX::FMOV32rr), DestReg) 58 BuildMI(MBB, I, DL, get(NVPTX::IMOV16rr), DestReg) 62 BuildMI(MBB, I, DL, get(NVPTX::IMOV64rr), DestReg) 66 BuildMI(MBB, I, DL, get(NVPTX::FMOV64rr), DestReg) 274 BuildMI(&MBB, DL, get(NVPTX::GOTO)).addMBB(TBB); 276 BuildMI(&MBB, DL, get(NVPTX::CBranch)) 282 BuildMI(&MBB, DL, get(NVPTX::CBranch)     [all...]
/external/llvm/lib/Target/Hexagon/
HexagonExpandPredSpillCode.cpp	90 BuildMI(*MBB, MII, MI->getDebugLoc(), 93 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_rr), 96 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd), 98 BuildMI(*MBB, MII, MI->getDebugLoc(), 103 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_ri), 105 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd), 107 BuildMI(*MBB, MII, MI->getDebugLoc(), 114 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd), 116 BuildMI(*MBB, MII, MI->getDebugLoc(), 134 BuildMI(*MBB, MII, MI->getDebugLoc()     [all...]
HexagonSplitTFRCondSets.cpp	107 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Opc1), 111 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Opc2), 126 BuildMI(*MBB, MII, MI->getDebugLoc(), 131 BuildMI(*MBB, MII, MI->getDebugLoc(), 136 BuildMI(*MBB, MII, MI->getDebugLoc(), 152 BuildMI(*MBB, MII, MI->getDebugLoc(), 157 BuildMI(*MBB, MII, MI->getDebugLoc(), 166 BuildMI(*MBB, MII, MI->getDebugLoc(), 182 BuildMI(*MBB, MII, MI->getDebugLoc(), 185 BuildMI(*MBB, MII, MI->getDebugLoc()     [all...]
HexagonRegisterInfo.cpp	176 BuildMI(*MI.getParent(), II, MI.getDebugLoc(), 178 BuildMI(*MI.getParent(), II, MI.getDebugLoc(), 182 BuildMI(*MI.getParent(), II, MI.getDebugLoc(), 205 BuildMI(*MI.getParent(), II, MI.getDebugLoc(), 207 BuildMI(*MI.getParent(), II, MI.getDebugLoc(), 211 BuildMI(*MI.getParent(), II, MI.getDebugLoc(), 225 BuildMI(*MI.getParent(), II, MI.getDebugLoc(), 227 BuildMI(*MI.getParent(), II, MI.getDebugLoc(), 234 BuildMI(*MI.getParent(), II, MI.getDebugLoc(), 243 BuildMI(*MI.getParent(), II, MI.getDebugLoc()     [all...]
HexagonFixupHwLoops.cpp	169 BuildMI(*MBB, MII, DL, TII->get(Hexagon::TFCR), Hexagon::LC0) 173 BuildMI(*MBB, MII, DL, TII->get(Hexagon::TFRI), Scratch) 175 BuildMI(*MBB, MII, DL, TII->get(Hexagon::TFCR), Hexagon::LC0) 179 BuildMI(*MBB, MII, DL, TII->get(Hexagon::CONST32_Label), Scratch) 181 BuildMI(*MBB, MII, DL, TII->get(Hexagon::TFCR), Hexagon::SA0)
/external/llvm/lib/Target/Sparc/
SparcFrameLowering.cpp	55 BuildMI(MBB, MBBI, dl, TII.get(SP::SAVEri), SP::O6) 61 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi); 63 BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1) 65 BuildMI(MBB, MBBI, dl, TII.get(SP::SAVErr), SP::O6) 81 BuildMI(MBB, I, dl, TII.get(SP::ADDri), SP::O6).addReg(SP::O6).addImm(Size); 94 BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
SparcInstrInfo.cpp	121 MachineInstrBuilder MIB = BuildMI(MF, dl, get(SP::DBG_VALUE)) 205 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(Opcode)) 207 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(SP::BA)) 240 BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB); 248 BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC); 250 BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC); 254 BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB); 285 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0) 288 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg) 291 BuildMI(MBB, I, DL, get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD), DestReg     [all...]
/external/llvm/lib/Target/Mips/
MipsLongBranch.cpp	223 MachineInstrBuilder MIB = BuildMI(MBB, Br, DL, NewDesc); 283 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP) 285 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)).addReg(Mips::RA) 289 .append(BuildMI(*MF, DL, TII->get(Mips::BAL_BR)).addMBB(BalTgtMBB)) 290 .append(BuildMI(*MF, DL, TII->get(Mips::LUi), Mips::AT).addImm(Hi)); 294 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::AT) 296 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDu), Mips::AT) 298 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LW), Mips::RA) 302 .append(BuildMI(*MF, DL, TII->get(Mips::JR)).addReg(Mips::AT)) 303 .append(BuildMI(*MF, DL, TII->get(Mips::ADDiu), Mips::SP     [all...]
Mips16InstrInfo.cpp	91 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc)); 112 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)) 129 BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(0) 180 BuildMI(MBB, I, DL, get(Mips::SaveRaF16)).addImm(FrameSize); 185 BuildMI(MBB, I, DL, get(Mips::SaveRaF16)). addImm(Base); 199 MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16), 203 MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16), 207 MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16), 222 BuildMI(MBB, I, DL, get(Mips::RestoreRaF16)).addImm(FrameSize); 231 BuildMI(MBB, I, DL, get(Mips::RestoreRaF16)). addImm(Base)     [all...]
/external/llvm/lib/Target/R600/
SILowerControlFlow.cpp	139 BuildMI(*From.getParent(), &From, DL, TII->get(AMDGPU::S_CBRANCH_EXECZ)) 156 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ)) 161 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::EXP)) 173 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_ENDPGM)); 182 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), Reg) 185 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), Reg) 200 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_SAVEEXEC_B64), Dst) 203 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), AMDGPU::EXEC) 219 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst) 234 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst     [all...]
/external/llvm/lib/Target/PowerPC/
PPCFrameLowering.cpp	151 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 155 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 160 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 164 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 169 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 173 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 177 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 361 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR8), PPC::X0); 364 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD)) 370 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD)     [all...]
PPCBranchSelector.cpp	161 BuildMI(MBB, I, dl, TII->get(PPC::BCC)) 164 BuildMI(MBB, I, dl, TII->get(PPC::BDZ)).addImm(2); 166 BuildMI(MBB, I, dl, TII->get(PPC::BDZ8)).addImm(2); 168 BuildMI(MBB, I, dl, TII->get(PPC::BDNZ)).addImm(2); 170 BuildMI(MBB, I, dl, TII->get(PPC::BDNZ8)).addImm(2); 176 I = BuildMI(MBB, I, dl, TII->get(PPC::B)).addMBB(Dest);
PPCInstrInfo.cpp	177 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc()) 201 BuildMI(MBB, MI, DL, get(PPC::NOP)); 385 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB); 387 BuildMI(&MBB, DL, get(Cond[0].getImm() ? 391 BuildMI(&MBB, DL, get(PPC::BCC)) 398 BuildMI(&MBB, DL, get(Cond[0].getImm() ? 402 BuildMI(&MBB, DL, get(PPC::BCC)) 404 BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB); 430 BuildMI(MBB, I, DL, MCID, DestReg) 433 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc))     [all...]
PPCRegisterInfo.cpp	213 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) 217 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg) 221 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) 229 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1) 234 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 239 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 244 BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1) 250 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 255 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 294 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFCR8pseud : PPC::MFCRpseud), Reg     [all...]
/external/llvm/lib/Target/XCore/
XCoreRegisterInfo.cpp	171 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg) 176 BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r)) 182 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg) 192 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg) 197 BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus)) 203 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg) 221 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) 226 BuildMI(MBB, II, dl, TII.get(NewOpcode)) 232 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) 252 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg).addImm(Value)     [all...]
XCoreInstrInfo.cpp	287 BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(TBB); 291 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()) 300 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()) 302 BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(FBB); 342 BuildMI(MBB, I, DL, get(XCore::ADD_2rus), DestReg) 349 BuildMI(MBB, I, DL, get(XCore::LDAWSP_ru6), DestReg).addImm(0); 354 BuildMI(MBB, I, DL, get(XCore::SETSP_1r)) 370 BuildMI(MBB, I, DL, get(XCore::STWFI)) 384 BuildMI(MBB, I, DL, get(XCore::LDWFI), DestReg) 393 MachineInstrBuilder MIB = BuildMI(MF, DL, get(XCore::DBG_VALUE)     [all...]
/external/llvm/lib/Target/MSP430/
MSP430FrameLowering.cpp	66 BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r)) 70 BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::FPW) 98 BuildMI(MBB, MBBI, DL, TII.get(MSP430::SUB16ri), MSP430::SPW) 135 BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::FPW); 156 BuildMI(MBB, MBBI, DL, 160 BuildMI(MBB, MBBI, DL, 170 BuildMI(MBB, MBBI, DL, TII.get(MSP430::ADD16ri), MSP430::SPW) 199 BuildMI(MBB, MI, DL, TII.get(MSP430::PUSH16r)) 220 BuildMI(MBB, MI, DL, TII.get(MSP430::POP16r), CSI[i].getReg()); 247 New = BuildMI(MF, Old->getDebugLoc()     [all...]
MSP430InstrInfo.cpp	51 BuildMI(MBB, MI, DL, get(MSP430::MOV16mr)) 55 BuildMI(MBB, MI, DL, get(MSP430::MOV8mr)) 79 BuildMI(MBB, MI, DL, get(MSP430::MOV16rm)) 82 BuildMI(MBB, MI, DL, get(MSP430::MOV8rm)) 100 BuildMI(MBB, I, DL, get(Opc), DestReg) 272 BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(TBB); 278 BuildMI(&MBB, DL, get(MSP430::JCC)).addMBB(TBB).addImm(Cond[0].getImm()); 283 BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(FBB);
/external/llvm/include/llvm/CodeGen/
MachineInstrBuilder.h	10 // This file exposes a function named BuildMI, which is useful for dramatically 13 // M = BuildMI(X86::ADDrr8, 2).addReg(argVal1).addReg(argVal2); 220 /// BuildMI - Builder interface. Specify how to create the initial instruction 223 inline MachineInstrBuilder BuildMI(MachineFunction &MF, 229 /// BuildMI - This version of the builder sets up the first operand as a 232 inline MachineInstrBuilder BuildMI(MachineFunction &MF, 240 /// BuildMI - This version of the builder inserts the newly-built 244 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, 255 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, 266 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB     [all...]
/external/llvm/lib/Target/MBlaze/
MBlazeFrameLowering.cpp	255 BuildMI(MENT, MENTI, ENTDL, TII.get(MBlaze::SWI), r) 263 BuildMI(MENT, MENTI, ENTDL, TII.get(MBlaze::SWI), MBlaze::R17) 266 BuildMI(MENT, MENTI, ENTDL, TII.get(MBlaze::SWI), MBlaze::R18) 272 BuildMI(MENT, MENTI, ENTDL, TII.get(MBlaze::MFS), MBlaze::R11) 274 BuildMI(MENT, MENTI, ENTDL, TII.get(MBlaze::SWI), MBlaze::R11) 277 BuildMI(MEXT, MEXTI, EXTDL, TII.get(MBlaze::LWI), MBlaze::R11) 279 BuildMI(MEXT, MEXTI, EXTDL, TII.get(MBlaze::MTS), MBlaze::RMSR) 284 BuildMI(MEXT, MEXTI, EXTDL, TII.get(MBlaze::LWI), MBlaze::R18) 287 BuildMI(MEXT, MEXTI, EXTDL, TII.get(MBlaze::LWI), MBlaze::R17) 293 BuildMI(MEXT, MEXTI, EXTDL, TII.get(MBlaze::LWI), r     [all...]
MBlazeInstrInfo.cpp	80 BuildMI(MBB, MI, DL, get(MBlaze::NOP)); 88 llvm::BuildMI(MBB, I, DL, get(MBlaze::ADDK), DestReg) 98 BuildMI(MBB, I, DL, get(MBlaze::SWI)).addReg(SrcReg,getKillRegState(isKill)) 108 BuildMI(MBB, I, DL, get(MBlaze::LWI), DestReg) 202 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB); 204 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()).addMBB(TBB); 208 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()).addMBB(TBB); 209 BuildMI(&MBB, DL, get(MBlaze::BRID)).addMBB(FBB); 291 BuildMI(FirstMBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY),
/external/llvm/lib/Target/ARM/
Thumb1InstrInfo.cpp	45 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) 73 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSTRspi)) 101 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg)
Thumb2RegisterInfo.cpp	48 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2LDRpci))
/external/llvm/lib/Target/AArch64/
AArch64InstrInfo.cpp	49 BuildMI(MBB, I, DL, get(AArch64::ADDxxi_lsl0_s), DestReg) 55 BuildMI(MBB, I, DL, get(AArch64::ADDwwi_lsl0_s), DestReg) 62 BuildMI(MBB, I, DL, get(AArch64::MSRix)) 68 BuildMI(MBB, I, DL, get(AArch64::MRSxi), DestReg) 80 BuildMI(MBB, I, DL, get(AArch64::FMOVss), DestReg) 85 BuildMI(MBB, I, DL, get(AArch64::FMOVdd), DestReg) 98 BuildMI(MBB, I, DL, get(AArch64::LSFP128_PreInd_STR), AArch64::XSP) 103 BuildMI(MBB, I, DL, get(AArch64::LSFP128_PostInd_LDR), DestReg) 113 BuildMI(MBB, I, DL, get(Opc), DestReg) 123 MachineInstrBuilder MIB = BuildMI(MF, DL, get(AArch64::DBG_VALUE)     [all...]

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