/external/llvm/include/llvm/MC/ |
MCInstBuilder.h | 33 Inst.addOperand(MCOperand::CreateReg(Reg));
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MCInst.h | 111 static MCOperand CreateReg(unsigned Reg) {
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/external/llvm/lib/Target/X86/Disassembler/ |
X86Disassembler.cpp | 167 mcInst.addOperand(MCOperand::CreateReg(llvmRegnum)); 378 mcInst.addOperand(MCOperand::CreateReg(X86::XMM0 + (immediate >> 4))); 381 mcInst.addOperand(MCOperand::CreateReg(X86::YMM0 + (immediate >> 4))); 444 mcInst.addOperand(MCOperand::CreateReg(X86::x)); break; 489 baseReg = MCOperand::CreateReg(X86::x); break; 494 baseReg = MCOperand::CreateReg(0); 535 indexReg = MCOperand::CreateReg(X86::x); break; 543 indexReg = MCOperand::CreateReg(0); 560 baseReg = MCOperand::CreateReg(X86::RIP); // Section 2.2.1.6 563 baseReg = MCOperand::CreateReg(0) [all...] |
/external/llvm/lib/Target/MBlaze/Disassembler/ |
MBlazeDisassembler.cpp | 541 instr.addOperand(MCOperand::CreateReg(RD)); 542 instr.addOperand(MCOperand::CreateReg(RB)); 543 instr.addOperand(MCOperand::CreateReg(RA)); 549 instr.addOperand(MCOperand::CreateReg(RD)); 550 instr.addOperand(MCOperand::CreateReg(RA)); 551 instr.addOperand(MCOperand::CreateReg(RB)); 557 instr.addOperand(MCOperand::CreateReg(RD)); 558 instr.addOperand(MCOperand::CreateReg(RA)); 568 instr.addOperand(MCOperand::CreateReg(RD)); 575 instr.addOperand(MCOperand::CreateReg(RA)) [all...] |
/external/llvm/lib/Target/Mips/Disassembler/ |
MipsDisassembler.cpp | 348 Inst.addOperand(MCOperand::CreateReg(Reg)); 359 Inst.addOperand(MCOperand::CreateReg(Reg)); 378 Inst.addOperand(MCOperand::CreateReg(Reg)); 390 Inst.addOperand(MCOperand::CreateReg(Reg)); 398 Inst.addOperand(MCOperand::CreateReg(RegNo)); 414 Inst.addOperand(MCOperand::CreateReg(Reg)); 417 Inst.addOperand(MCOperand::CreateReg(Reg)); 418 Inst.addOperand(MCOperand::CreateReg(Base)); 435 Inst.addOperand(MCOperand::CreateReg(Reg)); 436 Inst.addOperand(MCOperand::CreateReg(Base)) [all...] |
/external/llvm/lib/Target/ARM/ |
ARMInstrInfo.cpp | 41 NopInst.addOperand(MCOperand::CreateReg(0)); 44 NopInst.addOperand(MCOperand::CreateReg(ARM::R0)); 45 NopInst.addOperand(MCOperand::CreateReg(ARM::R0)); 47 NopInst.addOperand(MCOperand::CreateReg(0)); 48 NopInst.addOperand(MCOperand::CreateReg(0));
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Thumb1InstrInfo.cpp | 31 NopInst.addOperand(MCOperand::CreateReg(ARM::R8)); 32 NopInst.addOperand(MCOperand::CreateReg(ARM::R8)); 34 NopInst.addOperand(MCOperand::CreateReg(0));
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ARMAsmPrinter.cpp | [all...] |
ARMMCInstLower.cpp | 75 MCOp = MCOperand::CreateReg(MO.getReg());
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Thumb2ITBlockPass.cpp | 185 MI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/, 210 NMI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/,
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/external/llvm/lib/Target/Mips/AsmParser/ |
MipsAsmParser.cpp | 245 Inst.addOperand(MCOperand::CreateReg(getReg())); 267 Inst.addOperand(MCOperand::CreateReg(getMemBase())); 317 static MipsOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) { 347 Inst.addOperand(MCOperand::CreateReg(Reg.RegNum)); 354 Inst.addOperand(MCOperand::CreateReg(Reg.RegNum)); 362 Inst.addOperand(MCOperand::CreateReg(Reg.RegNum)); 370 Inst.addOperand(MCOperand::CreateReg(Reg.RegNum)); 374 Inst.addOperand(MCOperand::CreateReg(Reg.RegNum)); 431 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg())); 433 MCOperand::CreateReg(Mips::ZERO)) [all...] |
/external/llvm/lib/Target/X86/ |
X86InstrBuilder.h | 64 MO.push_back(MachineOperand::CreateReg(Base.Reg, false, false, 72 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false, 80 MO.push_back(MachineOperand::CreateReg(0, false, false,
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X86MCInstLower.cpp | 348 MCOp = MCOperand::CreateReg(MO.getReg()); 607 OutMI.addOperand(MCOperand::CreateReg(X86::R10)); 608 OutMI.addOperand(MCOperand::CreateReg(X86::RAX)); 651 LEA.addOperand(MCOperand::CreateReg(X86::RDI)); // dest 652 LEA.addOperand(MCOperand::CreateReg(X86::RIP)); // base 654 LEA.addOperand(MCOperand::CreateReg(0)); // index 656 LEA.addOperand(MCOperand::CreateReg(0)); // seg 659 LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest 660 LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // base 662 LEA.addOperand(MCOperand::CreateReg(0)); // inde [all...] |
/external/llvm/lib/Target/ARM/AsmParser/ |
ARMAsmParser.cpp | [all...] |
/external/llvm/lib/Target/R600/ |
AMDGPUMCInstLower.cpp | 54 MCOp = MCOperand::CreateReg(MO.getReg());
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/external/llvm/lib/Target/AArch64/Disassembler/ |
AArch64Disassembler.cpp | 246 Inst.addOperand(MCOperand::CreateReg(Register)); 257 Inst.addOperand(MCOperand::CreateReg(Register)); 268 Inst.addOperand(MCOperand::CreateReg(Register)); 279 Inst.addOperand(MCOperand::CreateReg(Register)); 290 Inst.addOperand(MCOperand::CreateReg(Register)); 301 Inst.addOperand(MCOperand::CreateReg(Register)); 313 Inst.addOperand(MCOperand::CreateReg(Register)); 324 Inst.addOperand(MCOperand::CreateReg(Register)); 336 Inst.addOperand(MCOperand::CreateReg(Register)); 347 Inst.addOperand(MCOperand::CreateReg(Register)) [all...] |
/external/llvm/include/llvm/CodeGen/ |
FunctionLoweringInfo.h | 136 unsigned CreateReg(MVT VT);
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/external/llvm/lib/Target/Hexagon/ |
HexagonMCInstLower.cpp | 58 MCO = MCOperand::CreateReg(MO.getReg());
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HexagonPeephole.cpp | 200 MI->addOperand(MachineOperand::CreateReg(PeepholeSrc, false)); 207 MI->addOperand(MachineOperand::CreateReg(PeepholeSrc.first,
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/external/llvm/lib/Target/MSP430/ |
MSP430MCInstLower.cpp | 123 MCOp = MCOperand::CreateReg(MO.getReg());
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/external/llvm/lib/Target/XCore/ |
XCoreMCInstLower.cpp | 90 return MCOperand::CreateReg(MO.getReg());
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/external/llvm/lib/Target/MBlaze/AsmParser/ |
MBlazeAsmParser.cpp | 195 Inst.addOperand(MCOperand::CreateReg(getReg())); 211 Inst.addOperand(MCOperand::CreateReg(getMemBase())); 215 Inst.addOperand(MCOperand::CreateReg(RegOff)); 236 static MBlazeOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) { 417 return MBlazeOperand::CreateReg(RegNo, StartLoc, EndLoc);
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/external/llvm/lib/Target/ARM/Disassembler/ |
ARMDisassembler.cpp | 628 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 633 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 695 MI.insert(I, MCOperand::CreateReg(0)); 697 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 705 MI.insert(I, MCOperand::CreateReg(0)); 707 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); [all...] |
/external/llvm/lib/Target/AArch64/ |
AArch64MCInstLower.cpp | 95 MCOp = MCOperand::CreateReg(MO.getReg());
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/external/llvm/lib/Target/MBlaze/ |
MBlazeMCInstLower.cpp | 127 MCOp = MCOperand::CreateReg(MO.getReg());
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