| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 247 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 },
249 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 3 },
251 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 },
265 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 },
267 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 4 },
269 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 8 },
283 { ISD::FP_TO_SINT, MVT::i1, MVT::f32, 2 },
285 { ISD::FP_TO_SINT, MVT::i1, MVT::f64, 2 },
287 { ISD::FP_TO_SINT, MVT::i8, MVT::f32, 2 },
289 { ISD::FP_TO_SINT, MVT::i8, MVT::f64, 2 }
[all...] |
| ARMISelLowering.cpp | 111 setOperationAction(ISD::FP_TO_SINT, VT, Custom);
116 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
562 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom);
595 setTargetDAGCombine(ISD::FP_TO_SINT);
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 391 FP_TO_SINT,
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 255 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 1 },
256 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 1 },
|
| X86ISelLowering.cpp | 295 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
298 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
300 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
301 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
304 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
306 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
308 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
309 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeFloatTypes.cpp | 612 case ISD::FP_TO_SINT: Res = SoftenFloatOp_FP_TO_SINT(N); break;
677 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_TO_SINT!");
[all...] |
| SelectionDAGDumper.cpp | 227 case ISD::FP_TO_SINT: return "fp_to_sint";
|
| LegalizeVectorTypes.cpp | 83 case ISD::FP_TO_SINT:
539 case ISD::FP_TO_SINT:
[all...] |
| LegalizeVectorOps.cpp | 226 case ISD::FP_TO_SINT:
|
| LegalizeDAG.cpp | [all...] |
| LegalizeIntegerTypes.cpp | 97 case ISD::FP_TO_SINT:
357 // not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT
362 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
363 NewOpc = ISD::FP_TO_SINT;
[all...] |
| FastISel.cpp | [all...] |
| SelectionDAGBuilder.cpp | [all...] |
| SelectionDAG.cpp | [all...] |
| DAGCombiner.cpp | [all...] |
| /external/llvm/lib/Target/R600/ |
| R600ISelLowering.cpp | 45 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Expand);
93 setTargetDAGCombine(ISD::FP_TO_SINT);
[all...] |
| AMDILISelLowering.cpp | 453 SDValue iq = DAG.getNode(ISD::FP_TO_SINT, DL, INTTY, fq);
|
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 722 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 234 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
235 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
236 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 194 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
195 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
285 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
407 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
[all...] |
| /external/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | [all...] |
