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  /external/llvm/lib/Target/Hexagon/
HexagonSubtarget.h 41 InstrItineraryData InstrItins;
48 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
HexagonTargetMachine.h 36 const InstrItineraryData* InstrItins;
55 return InstrItins;
HexagonSubtarget.cpp 65 InstrItins = getInstrItineraryForCPU(CPUString);
  /external/llvm/lib/Target/MBlaze/
MBlazeSubtarget.h 39 InstrItineraryData InstrItins;
62 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
MBlazeTargetMachine.h 39 InstrItineraryData InstrItins;
52 { return &InstrItins; }
MBlazeSubtarget.cpp 45 InstrItins = getInstrItineraryForCPU(CPUName);
MBlazeTargetMachine.cpp 45 InstrItins(Subtarget.getInstrItineraryData()) {
  /external/llvm/lib/Target/R600/
AMDGPUSubtarget.h 40 InstrItineraryData InstrItins;
46 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
AMDGPUTargetMachine.h 38 const InstrItineraryData* InstrItins;
62 return InstrItins;
AMDGPUSubtarget.cpp 26 InstrItins = getInstrItineraryForCPU(CPU);
  /external/llvm/include/llvm/CodeGen/
TargetSchedule.h 36 InstrItineraryData InstrItins;
77 return &InstrItins;
DFAPacketizer.h 46 const InstrItineraryData *InstrItins;
82 const InstrItineraryData *getInstrItins() const { return InstrItins; }
ResourcePriorityQueue.h 63 const InstrItineraryData* InstrItins;
  /external/llvm/lib/CodeGen/
TargetSchedule.cpp 36 return EnableSchedItins && !InstrItins.isEmpty();
60 STI->initInstrItins(InstrItins);
80 int UOps = InstrItins.getNumMicroOps(MI->getDesc().getSchedClass());
81 return (UOps >= 0) ? UOps : TII->getNumMicroOps(&InstrItins, MI);
189 TII->getOperandLatency(&InstrItins, DefMI, DefOperIdx, UseMI, UseOperIdx);
193 OperLatency = InstrItins.getOperandCycle(DefClass, DefOperIdx);
199 unsigned InstrLatency = TII->getInstrLatency(&InstrItins, DefMI);
202 // Rather than directly querying InstrItins stage latency, we call a TII
204 // applicable to the InstrItins model. InstrSchedModel should model all
253 return TII->getInstrLatency(&InstrItins, MI)
    [all...]
DFAPacketizer.cpp 36 InstrItins(I), CurrentState(0), DFAStateInputTable(SIT),
68 const llvm::InstrStage *IS = InstrItins->beginStage(InsnClass);
80 const llvm::InstrStage *IS = InstrItins->beginStage(InsnClass);
  /external/llvm/lib/Target/PowerPC/
PPCTargetMachine.h 38 InstrItineraryData InstrItins;
64 return &InstrItins;
PPCSubtarget.h 67 InstrItineraryData InstrItins;
115 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
PPCSubtarget.cpp 59 InstrItins = getInstrItineraryForCPU(CPUName);
  /external/llvm/lib/Target/ARM/
ARMTargetMachine.h 38 InstrItineraryData InstrItins;
54 return &InstrItins;
ARMSubtarget.h 176 InstrItineraryData InstrItins;
295 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
  /external/llvm/lib/Target/X86/
X86TargetMachine.h 35 InstrItineraryData InstrItins;
64 return &InstrItins;
  /external/llvm/lib/MC/
MCSubtargetInfo.cpp 115 void MCSubtargetInfo::initInstrItins(InstrItineraryData &InstrItins) const {
116 InstrItins =
  /external/llvm/lib/Target/Mips/
MipsSubtarget.cpp 46 InstrItins = getInstrItineraryForCPU(CPUName);
MipsSubtarget.h 98 InstrItineraryData InstrItins;
  /external/llvm/include/llvm/MC/
MCSubtargetInfo.h 134 void initInstrItins(InstrItineraryData &InstrItins) const;

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